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NDH8301N

Description
Dual N-Channel Enhancement Mode Field Effect Transistor
CategoryDiscrete semiconductor    The transistor   
File Size204KB,10 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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NDH8301N Overview

Dual N-Channel Enhancement Mode Field Effect Transistor

NDH8301N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codeunknow
ECCN codeEAR99
ConfigurationSEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage20 V
Maximum drain current (Abs) (ID)3 A
Maximum drain current (ID)3 A
Maximum drain-source on-resistance0.06 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
JESD-609 codee0
Number of components2
Number of terminals8
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)0.9 W
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal locationDUAL
transistor applicationsSWITCHING
Transistor component materialsSILICON
December 1996
NDH8301N
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such
as notebook computer power management, and other battery
powered circuits where fast switching, and low in-line power
loss are needed in a very small outline surface mount package.
Features
3 A, 20 V. R
DS(ON)
= 0.06
@ V
GS
= 4.5 V
R
DS(ON)
= 0.075
@ V
GS
= 2.7 V.
Proprietary SuperSOT
TM
-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
____________________________________________________________________________________________
5
4
3
2
1
6
7
8
Absolute Maximum Ratings
T
A
= 25°C unless otherwise note
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
Operating and Storage Temperature Range
(Note 1 )
(Note 1)
NDH8301N
20
8
3
15
0.8
-55 to 150
Units
V
V
A
W
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1)
(Note 1)
156
40
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDH8301N Rev.E

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