NDB7051L datasheet, PDF - EEWORLD Datasheet

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NDB7051L: DescriptionN-Channel Logic Level Enhancement Mode Field Effect Transistor; CategoryDiscrete semiconductor The transistor; File Size338KB，12 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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NDB7051L Overview

N-Channel Logic Level Enhancement Mode Field Effect Transistor

NDB7051L Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
package instruction	SMALL OUTLINE, R-PSSO-G2
Reach Compliance Code	unknow
ECCN code	EAR99
Other features	LOGIC LEVEL COMPATIBLE
Avalanche Energy Efficiency Rating (Eas)	430 mJ
Shell connection	DRAIN
Configuration	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	50 V
Maximum drain current (Abs) (ID)	68 A
Maximum drain current (ID)	67 A
Maximum drain-source on-resistance	0.0145 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
JEDEC-95 code	TO-263AB
JESD-30 code	R-PSSO-G2
JESD-609 code	e0
Number of components	1
Number of terminals	2
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	175 °C
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	N-CHANNEL
Maximum power dissipation(Abs)	130 W
Maximum pulsed drain current (IDM)	200 A
Certification status	Not Qualified
surface mount	YES
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal location	SINGLE
Maximum time at peak reflow temperature	NOT SPECIFIED
transistor applications	SWITCHING
Transistor component materials	SILICON

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September 1996

NDP7051L / NDB7051L

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

These logic level N-Channel enhancement mode power field

effect transistors are produced using Fairchild's proprietary,

high cell density, DMOS technology. This very high density

process has been especially tailored to minimize on-state

resistance, provide superior switching performance, and

withstand high energy pulses in the avalanche and

commutation modes. These devices are particularly suited for

low voltage applications such as automotive, DC/DC

converters, PWM motor controls, and other battery powered

circuits where fast switching, low in-line power loss, and

resistance to transients are needed.

Features

67 A, 50 V. R

DS(ON)

= 0.0145

Ω

@ V

= 5 V

DS(ON)

= 0.0115

Ω

@ V

= 10 V.

Low drive requirements allowing operation directly from logic

drivers. V

GS(TH)

< 2.0V.

Rugged internal source-drain diode can eliminate the need

for an external Zener diode transient suppressor.

175°C maximum junction temperature rating.

High density cell design for extremely low R

DS(ON)

TO-220 and TO-263 (D

PAK) package for both through hole

and surface mount applications.

________________________________________________________________________________

Absolute Maximum Ratings

Symbol

DSS

DGR

GSS

Parameter

Drain-Source Voltage

= 25°C unless otherwise noted

NDP7051L

±16

±25

200

130

0.87

-65 to 175

NDB7051L

Units

Drain-Gate Voltage (R

< 1 M

Ω

)

Gate-Source Voltage - Continuous

- Nonrepetitive (t

< 50 µs)

Drain Current

- Continuous

- Pulsed

Maximum Power Dissipation @ T

= 25°C

Derate above 25°C

W/°C

°C

STG

Operating and Storage Temperature Range

NDP7051L Rev.D/NDB7051L Rev.E

NDB7051L Related Products

	NDB7051L	NDP7051L
Description	N-Channel Logic Level Enhancement Mode Field Effect Transistor	N-Channel Logic Level Enhancement Mode Field Effect Transistor
Is it Rohs certified?	incompatible	incompatible
Maker	Fairchild	Fairchild
package instruction	SMALL OUTLINE, R-PSSO-G2	TO-220, 3 PIN
Reach Compliance Code	unknow	unknow
ECCN code	EAR99	EAR99

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