SaRonix
Crystal Clock Oscillator
Technical Data
Frequency Range:
Frequency Stability:
0.5 MHz to 106.25 MHz
±20, ±25, ±50 or ±100 ppm over all conditions: calibration
tolerance, operating temperature, input voltage change,
load change, 30 day aging, shock and vibration.
3.3V, LVCMOS / HCMOS, Tri-State
NTH / NCH Series
Temperature Range:
Operating:
Storage:
Supply Voltage:
Recommended Operating:
Supply Current:
ACTUAL SIZE
0 to +70°C or -40 to +85°C, See Part Numbering Guide
-55 to +125°C
3.3V ±10%
20mA
25mA
30mA
35mA
max, 0.5 to 30 MHz
max, 30+ to 50 MHz
max, 50+ to 80 MHz
max, 80+ to 106.25 MHz
Description
A crystal controlled, low current, low
jitter and high frequency oscillator with
precise rise and fall times demanded in
networking applications. The tri-state
function on the NTH enables the output
to go high impedance. Device is pack-
aged in a 14 or an 8-pin DIP compatible
resistance welded, all metal grounded
case to reduce EMI. True SMD DIL14
versions for IR reflow are available, se-
lect option "S" in part number builder.
See separate data sheet for SMD package
dimensions.
Applications & Features
•
•
•
•
•
•
•
•
•
•
•
ADSL, DSL
DS3, ES3, E1, STS-1, T1
Ethernet Switch, Gigabit Ethernet
Fibre Channel Controller
MPEG
Network Processors
Voice Over Packet
32 Bit Microprocessors
Tri-State output on NTH
LVCMOS / HCMOS compatible
Available up to 106.25 MHz
Output Drive:
HCMOS
Symmetry:
Rise and Fall Times:
45/55% max 0.5 to 70 MHz max
40/60% max @ 50% V
DD
4ns max 0.5 to 50 MHz, 20% to 80% V
DD
3ns max 50+ to 80 MHz
1.5ns max 80+ to 106.25 MHz
10% V
DD
max
90% V
DD
min
50 pF, 0.5 to 50 MHz
30pF, 50+ to 70 MHz
15pF, 70+ to 106.25 MHz
8ps max
Logic 0:
Logic 1:
Load:
Period Jitter RMS:
Mechanical:
Shock:
Solderability:
Terminal Strength:
Vibration:
Solvent Resistance:
Resistance to Soldering Heat:
Environmental:
Gross Leak Test:
Fine Leak Test:
Thermal Shock:
Moisture Resistance:
MIL-STD-883,
MIL-STD-883,
MIL-STD-883,
MIL-STD-883,
MIL-STD-202,
MIL-STD-202,
Method 2002, Condition B
Method 2003
Method 2004, Conditions A & C
Method 2007, Condition A
Method 215
Method 210, Condition A, B or C
MIL-STD-883,
MIL-STD-883,
MIL-STD-883,
MIL-STD-883,
Method
Method
Method
Method
1014, Condition C
1014, Condition A2
1011, Condition A
1004
Output Waveform
CMOS
T
r
Logic 1
80% V
DD
50% V
DD
20% V
DD
Logic 0
T
f
SYMMETRY
DS-159
REV D
SaRonix
141 Jefferson Drive • Menlo Park, CA 94025 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894
SaRonix
Crystal Clock Oscillator
Technical Data
Package Details
FULL SIZE PACKAGE
0.91
.036
max
21.0
max
.825
5.08
max
.200
.46±.08
.018±.003
15.24±.13
.600±.005
Pin 7
GND
6.35±0.51
0.25±0.02
3.3V, LVCMOS / HCMOS,
NTH / NCH Series
Part Numbering Guide
NTH 0 8 0 C
NTH
= Pin 1: Tri state, LVCMOS
NCH
= Pin 1: N/C, LVCMOS
Symmetry
0 = 40/60% max, 0 to 70°C
2 = 40/60% max, -40 to 85°C
A = 45/55% max, 0 to 70°C, 70 MHz max
C = 45/55% max, -40 to 85°C, 70 MHz max
Frequency Range
3 = 0.5 to 6 MHz
6 = 6+ to 24 MHz
8 = 24+ to 106.25 MHz
3 - 40.0000 (T)
Packing Method
(T) = Tape & Reel for SMD versions,
full reel increments only, 200pcs (full
size) or 250pcs (half size)
Blank = Bulk
Frequency (MHz)
3.3V Supply
Pin 1
Tri-State - NTH
N/C - NCH
13.0
max
.510
Pin 14
+3.3 VDC
(4) Glass
Insulators
7.75
max
.305
Pin 8
Output
Stability Tolerance
Package
C = ±100ppm
0 = Full Size, Thru-Hole
B = ±50ppm
9 = Half Size, Thru-Hole
A = ±25ppm, 0 to +70°C only
K = Full Size, Gull Wing
AA = ±20ppm, 0 to +70°C only
J = Half Size, Gull Wing
N = Half Size, Gull Wing, Spanked Leads
S = Full Size, True SMD Adaptor (see separate data sheet for dimensions)
Standard Marking Format
**
Includes Date Code, Frequency & Part Number
Tri-State Logic Table (NTH only)
Pin 1 Input
Logic 1 or NC
Logic 0 or GND
Pin 8 (5) Output
Oscillation
High Impedance
Required Input Levels on Pin 1:
Logic 1 = 2.2V min
Logic 0 = 0.8V max
SARONIX
XTAL OSC
Denotes Pin 1
HALF SIZE PACKAGE
13.0
max
.510
0.91
max
.036
5.08 max
.200
6.35±0.51
0.25±0.02
7.62±.20
.300±.008
Pin 4
GND
Output:
Output:
Internal Pullup Resistance
Control Input:
Oscillation @ V
IN
, 2.2V min
High Impedance @ V
IN
, 0.8V max
50KΩ min
Disable Output Delay: 100ns max
Test Circuit
.46±.08
.018±.003
Pin 1
Tri-State - NTH
N/C - NCH
1.5
.059
13.0
.510
max
120°
mA
M
TEST
POINT
Pin 14 (8)
V
DD
OUT
C
L
= 50 pF, 0.5 to 50 MHz
C
L
= 30 pF, 50+ to 70 MHz
C
L
= 15pF, 70+ to 106.25 MHz
(Note A)
Pin 8 (5)
120°
120°
7.62±.20
.300±.008
POWER
SUPPLY
VM
OSCILLATOR
GND
Pin 1 (1)
*
Pin 7 (4)
Pin 8
+3.3 VDC
1.7
.067
6.0
.236
Pin 5
Output
TRI-STATE INPUT (NTH only)
Standard Marking Format
**
Includes Date Code, Frequency & Part Number
NOTE A: C
L
includes probe and fixture capacitance
*( ) Indicates pin numbers for half-size package
SARONIX
Denotes Pin 1
All specifications are subject to change without notice.
**
Exact location of items may vary
DS-159
REV D
SaRonix
141 Jefferson Drive • Menlo Park, CA 94025 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894
FPGA/CPLD
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