NBLVEP16VR
2.5V/3.3V/5V ECL
Differential Receiver/Driver
with Oscillator Gain Stage
and Enabled High Gain
Outputs
The NBLVEP16VR is an ECL/LVPECL oscillator gain stage with
high−gain output buffers, selectable output enable and a feedback
buffer. The NBLVEP16VR is a solution for crystal oscillators and
SAW−based voltage−controlled oscillators.
•
Q and Q Outputs have Selectable 4 mA or 8 mA, Self Bias Current
Sources
•
QHG and QHG have a Selectable 10 mA, Self Bias Current Sources
•
Synchronous Output Enable of the High−Gain Outputs with
Selectable Disabled State
•
Selectable LVCMOS/LVTTL or LVPECL Level Input of the Output
Enable Pin
•
Maximum Frequency > 2.5 GHz Typical
•
(LV)PECL Mode Operating Range: V
CC
= 2.375 V to 5.5 V with
V
EE
= 0 V
•
NECL Mode Operating Range: V
CC
= 0 V with
V
EE
= −2.375 V to −5.5 V
•
Temperature Compensated Inputs and Outputs
•
Excellent Clock Input Sensitivity
•
V
BB
Output Supports Current Source/Sink Capability up to a
Robust 1.5 mA
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MARKING DIAGRAM
Bottom View
QFN−16
MN SUFFIX
CASE 485G
XXXX
A
L
Y
W
XXXX
XXXX
ALYW
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
NBLVEP16VRMN
NBLVEP16VRMNR2
Package
QFN−16
QFN−16
Shipping
†
123 / Rail
3000/ Tape &
Reel
Refer to
Note 1.
NBWLVEP16VR
Wafer
1. Contact Sales Representative.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
4 mA ea. (opt.) Brochure, BRD8011/D.
4 mA ea.
CS_SEL
V
EE
Q
Q
D
D
470
W
V
BB
V
BB_ADJ
OD_MODE
LEN Q
LATCH
D
470
W
0
V
BB
Q
Q
1
QHG
QHG
10 mA ea. (opt.)
V
EEP
EN
LVCMOS/LVTTL
Threshold
EN_SEL
Figure 1. Logic Diagram
©
Semiconductor Components Industries, LLC, 2003
1
December, 2003 − Rev. 2
Publication Order Number:
NBLVEP16VR/D
NBLVEP16VR
Exposed Pad
(EP)
Q
16
1
2
NBLVEP16VR
D
V
BB
3
4
5
EN
6
7
8
10
9
QHG
EN_SEL
Q
15
NC
14
V
CC
13
NC
OD_MODE
D
12
11
CS_SEL
QHG
D
V
BB
V
BB
OD_MODE
D
NBLVEP16VR
CS_SEL
Die: 1.16 x 1.19 mm
(x)
(y)
Bond Pad: 84
mm
Diameter
QHG
QHG
EN_SEL
V
EEP
V
CC
NC
Q
Q V
CC
EN V
BB_ADJ
V
EE
V
EE
V
BB_ADJ
V
EE
V
EEP
Figure 4. Die Map
Figure 3. Pinout Diagram
(Top View)
Table 4. PIN DESCRIPTION
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
OD_MODE*
D
D
V
BB
EN*
V
BB_ADJ
V
EE
V
EEP
EN_SEL
†
QHG
QHG
CS_SEL
V
CC
NC
Q
Q
EP
Positive Power Supply
No Connect
ECL / LVPECL Output
ECL / LVPECL Output
Power Supply (OPT)
LVCMOS / LVTTL Input (See Table 3)
ECL / LVPECL Output
ECL / LVPECL Output
Negative Power Supply
I/O
LVCMOS/LVTTL Input (See Table 3)
ECL / LVPECL Input
ECL / LVPECL Input
Reference Voltage Output
ECL / LVPECL or LVCMOS/LVTTL Input
(see Table 3)
Description
Selectable Mode of Output Disabled Level
Clock / Data Input
Inverted Clock / Data Input
Reference Voltage Output
Output Enable Synchronous with D and D
Adjust Standard V
BB
Levels Upward When Tied to V
CC
for
2.5 V Power Supply. Open for 3.3 V and 5 V Power Supply.
Negative Power Supply
Open or Tied to V
EE
(See Table 1) Optional 10mA Current
Source For QHG and QHG
Input LVEL Selector Pin for EN
Inverted High−Gain Output, Gain > 200
High−Gain Output, Gain > 200
Selects Q and Q Current Source Magnitude (see Table 1),
Open or Tied to V
EE
or V
CC
Positive Power Supply
No Connect
ECL/LVPECL Output for Feedback Loop
Inverted ECL/LVPECL Output for Feedback Loop
Exposed Pad on Package Bottom Should Only Be Con-
nected to V
EE
or Left Open
*Pins will default LOW when left open.
†Pin will default HIGH when left open.
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
3
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NBLVEP16VR
APPLICATIONS INFORMATION
The NBLVEP16VR is an ECL/LVPECL oscillator gain
stage with high−gain output buffers, selectable output
enable and a feedback buffer. The NBLVEP16VR is a
solution for crystal oscillators and SAW−based
voltage−controlled oscillators. Design versatility is
enhanced with EN, a synchronous output enable pin to
eliminate runt pulses; EN_SEL, an input state selector pin
offering LVCMOS/LVTTL or ECL/LVPECL level control
of EN; and OD_MODE, an output disable mode state pin
which selects the polarity of the high−gain output’s disabled
state.
The NBLVEP16VR Q and Q outputs are ideal for
feedback applications common in crystal oscillator gain
blocks. They each have a selectable on−chip pull−down
current source. External resistors may be used to increase the
pull−down current to a maximum of 25 mA. The QHG and
QHG outputs each have an optional on−chip pull−down
current source of 10 mA. When V
EEP
is left open, the 10 mA
output current sources are disabled and the QHG and QHG
outputs operate as standard ECL/LVPECL. When V
EEP
is
connected to V
EE
, the 10 mA current sources are activated.
The QHG and QHG pull−down current can be decreased by
using a resistor connect from V
EEP
to V
EE
. See current
source truth table for functions and options.
The output enable input pin, EN, is synchronized with the
D and D data input signals in a way that furnishes glitchless
gating of the QHG and QHG outputs and allows continuous
oscillator operation. For applications that require output
enable control, the NBLVEP16VR provides expanded
output enable selectability. The logic level of the input state
selector pin, EN_SEL, will determine whether the EN pin
accepts ECL/LVPECL or LVCMOS/LVTTL logic levels.
The output disable mode state pin, OD_MODE, adds
functional flexibility by giving the designer a choice of the
QHG outputs’ polarity when these high−gain outputs are
disabled. For example, with OD_MODE LOW and
EN LOW (LVPECL), the input is passed to the outputs and
the data output equals the data input. If the D input is LOW
when the EN goes HIGH, the next data transition to a HIGH
is ignored and QHG remains LOW and QHG remains
HIGH. The next positive transition of the data input is not
passed on to the QHG outputs under these conditions. The
QHG and QHG outputs remain in their disabled state as long
as the EN input is held HIGH. The EN input has no influence
on the Q or Q outputs and the data inputs are passed on to
these outputs whether EN is HIGH or LOW. When the data
input is HIGH and EN goes HIGH, it will force QHG LOW
and QHG HIGH on the next negative transition of the D
input. This configuration is ideal for crystal oscillator
applications where the oscillator can be free−running and
QHG/QHG gate on and off synchronously without adding
extra counts to the output. See truth table and timing diagram
for detailed ENable functions and options.
The NBLVEP16VR provides a V
BB
and internal 470
W
bias resistors from D to V
BB
and D to V
BB
for ac coupled
single−ended or differential input signal(s). The V
BB_ADJ
pin is used for 2.5 V single−ended operation when it is
connected to V
CC
. The V
BB
output current source/sink
capability can support a robust 1.5 mA.
For single−ended input conditions, the unused differential
input is internally connected to V
BB
as a switching reference
voltage. Decouple V
BB
and V
CC
with a 0.01
mF
capacitor.
This internal V
BB
will rebias AC coupled input(s). Inputs D
or D must be signal driven or auto oscillation may result.
D
D
(PECL)
EN_SEL HIGH (OPEN)
EN
EN_SEL LOW
(CMOS) (SHORTED TO V
EE
)
OD_MODE
Q
Q
QHG
QHG
Figure 5. Timing Diagram
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4
NBLVEP16VR
ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
> 2 kV
> 150 V
> 1 kV
Level 1
UL 94 V−0 @ 0.125 in
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
BB
I
IN
I
out
T
A
T
stg
q
JA
q
JC
LVPECL Mode Power Supply
NECL Mode Power Supply
LVPECL Mode Input Voltage
NECL Mode Input Voltage
V
BB
Current Sink/Source
Input Current (V
IN
− V
BB
)
B
470
W
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
0 LFPM
500 LFPM
Standard Board
D, D
Continuous
Surge
Parameter
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Rating
6
−6
6
−6
$1.5
$5
50
100
−40 to +85
−65 to +150
Unit
V
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum−rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
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5
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