Integrated
Circuit
Systems, Inc.
ICS93716
Low Cost DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I
2
C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
•
Bypass mode on B revision only
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <75ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 550ps - 950ps
Pin Configuration
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
CLKT2
CLKC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
FBINC
FBINT
FB_OUTT
FB_OUTC
CLKT3
CLKC3
GND
28-Pin SSOP and TSSOP
Functionality
INPUTS
AVDD CLK_INT
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
L
H
<20MHz
L
H
H
L
CLK_INC CLKT CLKC
H
L
L
H
Z
L
H
H
L
Z
H
L
OUTPUTS
FB_OUTT FB_OUTC
L
H
Z
L
H
H
L
Z
H
L
PLL State
on
on
off
Bypassed/off
Bypassed/off
Block Diagram
GND
GND
FB_OUTT
FB_OUTC
SCLK
SDATA
Control
Logic
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
FB_INT
FB_INC
CLK_INC
CLK_INT
CLKT3
CLKC3
PLL
CLKT4
CLKC4
CLKT5
CLKC5
0420H—09/10/08
ICS93716
ICS93716
Pin Descriptions
PIN NUMBER
6, 11, 15, 28
PIN NAME
GND
TYPE
PWR
OUT
OUT
PWR
Ground
"Complementar y" clocks of differential pair outputs.
"Tr ue" Clock of differential pair outputs.
Power supply 2.5V
DESCRIPTION
27, 25, 16, 14, 5, 1 CLKC(5:0)
26, 24, 17, 13, 4, 2 CLKT(5:0)
3, 12, 23
7
8
9
10
18
VDD
SCLK
CLK_INT
CLK_INC
VDDA
FB_OUTC
IN
IN
IN
PWR
OUT
Clock input of I
2
C input, 5V tolerant input
"True" reference clock input
"Complementar y" reference clock input
Analog power supply, 2.5V
"Complementar y" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementar y" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
19
20
21
22
FB_OUTT
FB_INT
FB_INC
OUT
IN
IN
SDATA
IN
Data input for I
2
C serial input, 5V tolerant input
0420H—09/10/08
2
ICS93716
Byte 0: Output Control
(1= enable, 0 = disable)
Byte 1: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
2, 1
4, 5
-
-
13, 14
26, 27
-
24, 25
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
CLKT0, CLKC0
CLKT1, CLKC1
Reserved
Reserved
CLKT2, CLKC2
CLKT5, CLKC5
Reserved
CLKT4, CLKC4
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
17, 16
-
-
-
-
-
-
PWD
X
1
X
X
X
X
X
X
DESCRIPTION
Reserved
CLKT3, CLKC3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 2: Reserved
(1= enable, 0 = disable)
Byte 3: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reser ved
BIT PIN# PWD
Bit 7
-
X
Bit 6
-
X
Bit 5
-
X
Bit 4
-
X
Bit 3
-
X
Bit 2
-
X
Bit 1
-
X
Bit 0
-
X
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reser ved
Byte 4: Reserved
(1= enable, 0 = disable)
Byte 5: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reser ved
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN# PWD
-
0
-
0
-
0
-
0
-
0
-
1
-
1
-
0
DESCRIPTION
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
0420H—09/10/08
3
ICS93716
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
-0.5V to 4.6V
GND - 0.5V to V
DD
+ 0.5V
0°C to +85°C
-65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120Ω, C
L
=15pF (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
Operating Supply
Current
Input Clamp Voltage
High-level output
voltage
Low-level output voltage
SYMBOL
CONDITIONS
I
IH
V
I
= V
DD
or GND
I
IL
V
I
= V
DD
or GND
I
DD2.5
R
L
= 120Ω, C
L
= 0pf @ 170MHz
I
DDPD
V
IK
V
OH
V
OL
C
L
= 0pf
V
DDQ
= 2.3V Iin = -18mA
I
OH
= -1 mA
I
OH
= -12 mA
I
OL
=1 mA
I
OL
=12 mA
V
I
= GND or V
DD
V
OUT
= GND or V
DD
MIN
5
TYP
MAX
5
250
65
V
DD
- 0.1
1.7
0.1
0.6
3
3
350
90
-1.2
UNITS
µA
µA
mA
mA
V
V
V
V
V
pF
pF
C
IN
Input Capacitance
1
C
OUT
Output Capacitance
1
1
Guaranteed by design at 233MHz, not 100% tested in production.
0420H—09/10/08
4
ICS93716
DC Electrical Characteristics
(see note1)
T
A
= 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
Low level input voltage
SYMBOL
V
DDQ
, A
VDD
V
IL
CONDITIONS
MIN
2.3
TYP
2.5
0.4
MAX
2.7
V
DD
/2 - 0.18
0.7
2.1
5
V
DD
+ 0.3
V
DD
+ 0.6
V
DD
+ 0.6
V
DD
/2 + 0.15
V
DD
/2
0.1
0
V
DD
/2 + 0.2
±5
85
UNITS
V
V
V
V
V
V
V
V
V
V
µA
°C
High level input voltage
DC input signal voltage
(note 2)
Differential input signal
voltage (note 3)
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High Impedance
Output Current
Operating free-air
temperature
V
IH
V
IN
CLK_INT, CLK_INC, FB_INC,
FB_INT
SCLK, SDATA
-0.3
CLK_INT, CLK_INC, FB_INC,
V
DD
/2 + 0.18
FB_INT
SCLK, SDATA
1.7
-0.3
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36
0.7
V
DD
/2 - 0.15
V
DD
/2 - 0.2
V
DD
=2.7V, V
OUT
=V
DD
or GND
V
ID
V
OX
V
IX
I
OZ
T
A
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC excursion of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DD
and is the
voltage at which the differential signal crosses.
0420H—09/10/08
5
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