®
EMIF09-02726Sx
EMI FILTER
INCLUDING ESD PROTECTION
Application Specific Discretes
A.S.D.
TM
MAIN APPLICATIONS
Where EMI filtering in ESD sensitive equipment is
required :
Computers and printers
Communication systems
Mobile phones
MCU Boards
SO-20
DESCRIPTION
The EMIF09-02726sx is a highly integrated array
designed to suppress EMI / RFI noise in all
systems
subjected
to
electromagnetic
interferences.
Additionally, this filter includes an ESD protection
circuitry which prevents the protected device from
destruction when subjected to ESD surges up to
15 kV.
BENEFITS
Cost-effectiveness compared to discrete
solution
EMI bi-directional low-pass filter
High efficiency in ESD suppression.
High reliability offered by monolithic integration
COMPLIESWITH THE FOLLOWING STANDARD:
I
SSOP20
PIN-OUT CONFIGURATION
I1
I2
I3
I4
I5
GND
I6
I7
I8
I9
O1
O2
O3
9
C
E
L
L
S
O4
O5
GND
O6
O7
O8
O9
IEC 1000-4-2
15kV
8 kV
(air discharge)
(contact discharge)
O
D
D
R
I/O
= 27
Ω
, tolerance +/-20%
EMIF09-02726Sxfiltering response curves
C
IN
= 130pF
Typical response to IEC1000-4-2
(16 kV air discharge)
ASD is a trademark of STMicroelectronics
August 1999 - Ed: 2
1/12
EMIF09-02726Sx
ABSOLUTE MAXIMUM RATINGS
(T
amb
=
25°C)
Symbol
V
PP
Parameter
Maximum electrostatic discharge in following
measurement conditions:
MIL STD 883C - METHOD 3015-6
IEC1000-4-2 - air discharge
IEC1000-4-2 - contact discharge
Peak pulse power (8/20
µ
s)
Storage temperature range
Junction temperature
Operating temperature range
Value
Unit
25
16
9
200
- 55 to + 150
150
- 40 to + 85
kV
P
PP
T
stg
T
j
T
OP
W
°C
°
C
°C
Symbol
V
RM
V
BR
V
CL
V
F
C
IN
Rd
I
RM
I
PP
Parameter
Stand-offvoltage
Breakdown voltage
Clamping voltage
Forward voltage drop
Input capacitance per line
Dynamic impedance
Leakage current
Peak pulse current
Slope = 1 / Rd
I
I
F
V
BR
V
F
V
CL
V
RM
I
RM
V
I
PP
Symbol
I
RM
V
BR
V
F
Rd
C
Test conditions
V
RM
= 5.25 V, between any I/O pin and GND
I
R
= 1 mA, between any I/O pin and GND
IF = 200 mA, between any I/O pin and GND
I
PP
= 15 A, t
p
= 2.5µs (note 2)
0V bias V
RMS
= 30mV
F = 1MHz (note 3)
Min.
6.1
Typ.
Max.
20
7.2
1.25
Unit
µ
A
V
V
Ω
pF
0.3
130
Note 1:
V
CL
corresponds to the voltage level seen at the output pin
Note 2:
Rd is given per diode
Note 3:
C is given per diode
2/12
EMIF09-02726Sx
Fig. 1:
Peak power dissipation versus initial junc-
tion temperature.
Ppp[Tj initial]/Ppp[Tj initial=25°C]
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2000
1000
Fig. 2:
Peak pulse power versus exponentialpulse
duration (Tj initial=25°C).
Ppp(W)
100
Tj initial(°C)
tp(µs)
10
0
25
50
75
100
125
150
1
10
100
Fig. 3:
Clamping voltage versus peak pulse cur-
rent (Tj initial=25°C).
Rectangular waveform: tp = 2.5
µ
s
30.0
10.0
Ipp(A)
tp=2.5µs
Output Vcl
Input Vcl
Fig. 4:
Input capacitance versus reverse applied
voltage (typical values).
C(pF)
220
200
180
160
F=1MHz
Vosc=30mV
1.0
140
120
VR(V)
1
2
5
10
Vcl(V)
0.1
5
6
7
8
9
10
11
12
13
14
15
100
Fig. 5:
Relative variation of leakagecurrent versus
junction temperature (typical values).
Fig. 6:
Peak forward voltage drop versus peak for-
ward current (typical values).
Rectangular waveform: tp = 2.5µs
IFM(A)
IR[Tj] / IR[Tj=25°C]
3.0
2.5
1.00
2.0
1.5
1.0
0.5
0.0
25
50
75
Tj(°C)
100
125
150
0.10
5.00
VFM(V)
0.01
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
3/12
EMIF09-02726Sx
ESD protection by the EMIF09-02726Sx
Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
Transient Voltage Suppressors are an ideal choice for ESD protection. They are capable of clamping the
incoming transient to a low enough level such that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As the transient
rises above the operatingvoltage of the device, the TVS array becomes a low impedancepath diverting the
transient current to ground.
Fig. 7:
Example of connectionfor one cell of the EMIF09-02726Sx
I1
I2
I3
I4
I5
GND
I6
I7
O1
O2
O3
O4
O5
GND
O6
O7
EMIF09-02726Sx
O8
O9
Logic
Transceiver
I8
I9
1284-A
Connector
The EMIF09-02726Sx array is the ideal board level protection of ESD sensitive semiconductor
components. It provides best efficiency when using separated inputs and outputs, in the so called 4-points
structure.
Circuit Board Layout
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
The EMIF09-02726Sx should be placed as near as possible to the input terminals or connectors.
The path length between the ESD suppressor and the protectedline should be minimized.
All conductive loops, including power and ground loops should be minimized.
The ESD transient return path to ground should be kept as short as possible.
Ground planes should be used whenever possible.
Fig. 8:
Recommended PCB layout to benefit from 4-point structure
TO DO
I1
I2
I3
I4
I5
GND
I6
O 1
I2
O 2
I3
O 3
I4
O 4
I5
O 5
GND
GND
I6
O 6
O 7
O 8
O 9
O6
O7
O8
O9
GND
O5
O4
O3
O2
NOT TO DO
I1
O1
Logic
Transceiv
er,
ASIC,...
I7
I8
I9
Logic
Transceiv
er,
ASIC,...
I7
I8
I9
EMIF09-02726Sx
footprint
4/12
EMIF09-02726Sx
footprint
EMIF09-02726Sx
TECHNICAL INFORMATION
ESD PROTECTION
The EMIF09-02726Sx is particularly optimized to perform high level ESD protection. The clamping voltage
is given by the formula:
V
CL
= V
br
+ R
d
.I
PP
The protection function is splitted in 2 stages. As shown in figure A1, the ESD strike is clamped by the first
stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a
configuration makes the output voltage very low at the Vout level.
Fig. A1:
ESD clamping behavior
Rg
Rd
Vg
Vin
Vbr
S1
Vbr
S2
Device to be protected
R
Rd
Vout
Rload
ESD
Surge
EMIF09-02726Sx
To determine the remaining voltages at both Vin and Vout stages, we give the typical dynamic resistance
value Rd. Considering that : R>>Rd, Rg>>Rd and Rload>>Rd, the voltages are given by the following
formulas:
R
g
.V
br
+
R
d
.V
g
Vin
=
R
g
Vout
=
R.V
br
+
R
d
.Vin
R
The result of the calculation made for V
G
= 8kV, Rg= 330
Ω
(IEC1000-4-2 standard), V
br
=6.6V, Rd=0.3
Ω
and R=27
Ω
is:
Vin = 13.87V
Vout = 6.75 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side because the
current involved after the resistance R is low.
5/12
京公网安备 11010802033920号
EEWORLD
