INTEGRATED CIRCUITS
74F564
Octal D flip-flop (3-State)
Product specification
IC15 Data Handbook
1996 Jan 05
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
FEATURES
•
74F564 is broadside pinout version of 74F534
•
Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
PIN CONFIGURATION
OE 1
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
•
Useful as an Input or Ouput port for Microprocessors
•
3-State Ouputs for Bus interfacing
•
Common Output Enable
•
74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC
board layout and allows easy interface with microprocessors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the register operation. When OE is Low, data in the
register appears at the outputs. When OE is High, the outputs are in
high impedance “off” state, which means they will neither drive nor
load the bus.
GND 10
SF01052
TYPE
74F564
TYPICAL f
MAX
180MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
50mA
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic DIP
20-Pin Plastic SOL
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F564N
N74F564D
PKG.
DWG #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 - D7
OE
CP
Data inputs
Output Enable input (active Low)
Clock Pulse input (active rising edge)
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
Q0 - Q7
3-State outputs
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
2
3
4
5
6
7
8
9
LOGIC SYMBOL (IEEE/IEC)
1
11
C2
D1
D2
D3
D4
D5
D6
D7
EN1
D0
11
CP
2
3
4
2D
1
19
18
17
16
15
14
13
12
1
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
5
6
7
19
18
17
16
15
14
13
12
8
9
V
CC
=Pin 20
GND=Pin 10
SF01053
SF01054
1996 Jan 05
2
853-0166 16189
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
LOGIC DIAGRAM
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
CP
11
OE
1
19
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
V
CC
=Pin 20
GND=Pin 10
Q0
SF01055
FUNCTION TABLE
INPUTS
OE
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
CP
↑
↑
↑
↑
↑
Dn
l
h
X
X
Dn
INTERNAL
REGISTER
L
H
NC
NC
Dn
OUTPUTS
Q0 – Q7
H
L
NC
Z
Z
OPERATING MODES
Load and read register
Hold
Disable outputs
High voltage level
High voltage level one setup time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one setup time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5.0
–0.5 to +V
CC
48
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
1996 Jan 05
3
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
LIMITS
MIN
4.5
2.0
0.8
–18
–3
24
70
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
NO TAG
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
MIN
2.4
2.7
3.4
0.35
0.35
–0.73
0.50
0.50
–1.2
100
20
–0.6
50
–50
–60
45
V
CC
= MAX
50
55
–150
65
75
80
TYP
NO TAG
MAX
UNIT
V
V
V
V
V
µA
µA
mA
µA
µA
mA
mA
mA
mA
V
O
OH
High-level
High level output voltage
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
O
= 2.7V
V
CC
= MAX, V
O
= 0.5V
V
CC
= MAX
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Low-level
Low level output voltage
Input clamp voltage
Input current at
maximum input voltage
High-level input current
Low-level input current
Off-state output current,
High-level voltage applied
Off-state output current,
Low-level voltage applied
Short-circuit output current
NO TAG
I
CCH
Supply current (total)
I
CCL
I
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
1996 Jan 05
4
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
T
amb
= +25°C
V
CC
= +5V
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock frequency
Propagation delay
CP to Qn
Output Enable time
to High or Low level
Output Disable time
from High or Low level
Waveform
NO TAG
Waveform
NO TAG
Waveform 4
Waveform 5
Waveform 4
Waveform 5
160
3.5
3.5
2.5
4.0
1.0
1.0
TYP
180
5.0
5.0
4.5
5.5
3.0
2.5
8.0
8.0
7.5
8.0
6.0
5.5
MAX
T
amb
= 0°C to +70°C
V
CC
= +5V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
150
3.0
3.0
2.0
3.5
1.0
1.0
8.5
8.5
8.0
8.5
7.0
6.0
MAX
MHz
ns
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
T
amb
= +25°C
V
CC
= +5V
C
L
= 50pF, R
L
= 500Ω
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time,
Dn to CP
Hold time,
Dn to CP
CP pulse width,
High or Low
Waveform 3
Waveform 3
Waveform NO TAG
2.0
2.0
1.0
1.0
3.5
3.5
TYP
MAX
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
2.0
2.5
1.5
1.5
3.5
3.5
MAX
ns
ns
ns
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
Dn
CP
V
M
t
W
(H)
t
PHL
Qn
V
M
V
M
t
W
(L)
t
PLH
V
M
Qn
V
M
V
M
V
M
V
M
t
PHL
V
M
t
PLH
SF01051
SF00990
Waveform 1. Propagation Delay, Clock and Enable Inputs
to Output, Enable, Clock Pulse Widths,
and Maximum Clock Frequency
Waveform 2. Propagation Delay for Data to Outputs
1996 Jan 05
5
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