IDT71V67803 datasheet, PDF - EEWORLD Datasheet

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IDT71V67803: Description256K X 36 CACHE SRAM, 4.2 ns, PQFP100; Categorystorage; File Size515KB，23 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT71V67803 Overview

256K X 36 CACHE SRAM, 4.2 ns, PQFP100

IDT71V67803 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Minimum operating temperature	-40 Cel
Maximum operating temperature	85 Cel
Rated supply voltage	3.3 V
Minimum supply/operating voltage	3.14 V
Maximum supply/operating voltage	3.46 V
Processing package description	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
each_compli	Yes
EU RoHS regulations	Yes
state	Active
ccess_time_max	4.2 ns
jesd_30_code	R-PQFP-G100
jesd_609_code	e3
storage density	9.44E6 bi
Memory IC type	CACHE SRAM
memory width	36
moisture_sensitivity_level	3
Number of digits	262144 words
Number of digits	256K
operating mode	SYNCHRONOUS
organize	256KX36
Packaging Materials	PLASTIC/EPOXY
ckage_code	LQFP
packaging shape	RECTANGULAR
Package Size	FLATPACK, LOW PROFILE
serial parallel	PARALLEL
eak_reflow_temperature__cel_	260
qualification_status	COMMERCIAL
seated_height_max	1.6 mm
surface mount	YES
Craftsmanship	CMOS
Temperature level	INDUSTRIAL
terminal coating	MATTE TIN
Terminal form	GULL WING
Terminal spacing	0.6500 mm
Terminal location	QUAD
ime_peak_reflow_temperature_max__s_	30
length	20 mm
width	14 mm
dditional_feature	PIPELINED ARCHITECTURE

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256K X 36, 512K X 18

3.3V Synchronous SRAMs

3.3V I/O, Burst Counter

Pipelined Outputs, Single Cycle Deselect

IDT71V67603

IDT71V67803

Features

256K x 36, 512K x 18 memory configurations

Supports high system speed:

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW byte

GW),

write enable (BWE and byte writes (BW

BWE),

BWx)

BWE

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O supply (V

DDQ

)

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

Description

The IDT71V67603/7803 are high-speed SRAMs organized as

256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,

data, address and control registers. Internal logic allows the SRAM to

generate a self-timed write based upon a decision which can be left until

the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V67603/7803 can provide four cycles of

data for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-

pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165

fine pitch ball grid array (fBGA).

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5310 tbl 01

NOTE:

and

are not applicable for the IDT71V67802.

SEPTEMBER 2004

DSC-5310/06

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