DAE-KDNA-41M6571440 datasheet, PDF

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DAE-KDNA-41M6571440: DescriptionPhase Locked Loop, CQCC16, SMD-16; CategoryAnalog mixed-signal IC The signal circuit; File Size1022KB，12 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

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DAE-KDNA-41M6571440 Overview

Phase Locked Loop, CQCC16, SMD-16

DAE-KDNA-41M6571440 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Vectron International, Inc.
package instruction	QCCN, LCC16,.2X.3,40
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CQCC-N16
length	7.49 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Encapsulate equivalent code	LCC16,.2X.3,40
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Maximum seat height	2.13 mm
Maximum supply current (Isup)	63 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	1.02 mm
Terminal location	QUAD
width	5.08 mm
Base Number Matches	1

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CD-700

Complete VCXO Based Phase Lock Loop

CD-700

Description

The VI CD-700 is a user-con gurable crystal based PLL integrated circuit. It includes a digital phase detector, op-amp, VCXO

and additional integrated functions for use in digital synchronization applications. Loop lter software is available as well SPICE

models for circuit simulation.

Features

•

5 x 7.5 x 2 mm, smallest VCXO PLL available

Output Frequencies to 77.76 MHz

5.0 or 3.3 Vdc operation

Tri-State Output

Holdover on Loss of Signal Alarm

VCXO with CMOS outputs

0/70 or –40/85 C temperature range

Hermetically sealed ceramic SMD package

Product is compliant to RoHS directive

•

Applications

Frequency Translation

Clock Smoothing, Clock Switching

NRZ Clock recovery

DSLAM, ADM, ATM, Aggregation, Optical Switching/Routing,

Base Station

Synchronous Ethernet

Low jitter PLL’s

Block Diagram

LOS

(8)

PHO OPN

(3)

(2)

OPOUT VC

(1)

(16)

LOSIN

(4)

DATAIN

(5)

CLKIN

(6)

Phase Detector and

LOS

VCXO

OUT1

(13)

Optional 2nd divider

OUT2

(11)

RCLK

(9)

RDATA

(10)

OPP

(15)

GND VDD

(7) (14)

HIZ

(12)

Page 1 of 12

CD-700 Theory of Operation

Phase Detector

The phase detector has two bu ered inputs (DATAIN and CLKIN) which are designed to switch at 1.4 volts. DATAIN is designed to

accept an NRZ data stream but may also be used for clock signals which have a 50% duty cycle. CLKIN is connected to OUT1 or

OUT2, or a divided version of one of these outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the

power supply voltage or ground by more than a few hundred millivolts.

The phase detector is basically a latched ip op/exclusive-or gate/di erential ampli er lter design to produce a DC signal

proportional to the phase between the CLKIN and DATAIN signals (see Figure 4 for a block diagram and Figure 5 for an open loop

transfer curve). This will simplify the PLL design as the designer does not have to lter narrow pulse signals to a DC level. Under

locked conditions the rising edge of CLKIN will be centered in the middle of the DATAIN signal (see Figure 6).

The phase detector gain is 0.53V/rad x data density for 5volt

operation and 0.35V/rad x data density for 3.3 volt opera-

tion. Data density is equal to 1.0 for clock signals and is

system dependent on coding and design for NRZ signals,

but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN fre-

quencies greater than 1 MHz but produces signi cant ripple

when inputs are less than 200 kHz. Additional ltering is

required for lower input frequencies applications such as

8kHz (see Figures 8 and 9 as examples).

Figure 4. Simpli ed Phase Detector Block Diagram

Under closed loop conditions the active lter has a block-

ing capacitor which provides a very high DC gain, so under

normal locked conditions and input frequencies >1 MHz, PHO will be about VDD/2 and will not vary signi cantly with changes in

input frequency (within lock range). The control voltage (pin 16) will vary according to the input frequency o set, but PHO will

remain relatively constant.

Recovered Clock and Data Alignment

Outputs

The CD-700 is designed to recover an embedded clock from

an NRZ data signal and retime it with a data pattern. In this

application, the VCXO frequency is exactly the same frequency

as the NRZ data rate and the outputs are taken o Pin 9 (RCLK),

and Pin 10 (RDATA). Under locked conditions, the falling edge of

RCLK is centered in the RDATA pattern. Also, there is a 1.5 clock

cycle delay between DATAIN and RDATA. Figure 6 shows the

relationship between the DATAIN, CLKIN, RDATA and RCLK.

Figure 5. Open Loop Phase Detecto Transfer Curve

Figure 6. Clock and Data Timing Relationships for the NRZ data

Other RZ encoding schemes such as Manchester or AMI can be accomodated by using a CD-700 at twice the baud rate.

Page 4 of 12

Loss of Signal, LOS and LOSIN

The LOS circuit provides an output alarm ag when the DATAIN input signal is lost. The LOS output is normally a logic low

and is set to a logic high after 256 consecutive clock periods on CLKIN with no detected DATAIN transitions. This signal can be

used to either ag external alarm circuits and/or drive the CD-700’s LOSIN input. When LOSIN is set to a logic high, the VCXO

control voltage (pin 16) is switched to an internal voltage which sets OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS

automatically closes the op amp feedback which means the op-amp is a unity gain bu er and will produce a DC voltage equal to

the +op amp voltage (pin 15), usually VDD/2.

VCXO and Absolute Pull Range (APR) Speci cation

The CD-700’s VCXO is a varactor tuned crystal oscillator, which produces an output frequency proportional to the control voltage

(pin 16). The frequency deviation of the CD-700 VCXO is speci ed in terms of Absolute Pull Range (APR). APR provides the user

with a guaranteed speci cation for minimum available frequency deviation over all operating conditions. Operating conditions

include power supply variation, operating temperature range, and di erences in output loading and changes due to aging.

A CD-700 VCXO with an APR of +/-50 ppm will track a +/-50 ppm reference source over all operating conditions. The fourth

character of the product code in Table 7 speci es absolute Pull Range (APR). Please see Vectron’s web site (www.vectron.com) for

the APR Application Note. APR is tested at 0.5 and 4.5 volts for the 5.0 volt option and 0.3 and 3.0 volts for the 3.3 volt option.

VCXO Aging

Quartz oscillators typically exhibit a part per million shift in output frequency during aging. The major factors, which lead to this

shift, are changes in the mechanical stress on the crystal and mass-loading on the crystal.

As the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through the package to the

crystal mounting arrangement can lead to frequency variations. VI has minimized these two e ects through the use of a miniature

AT-cut strip resonator crystal which allows a superior mounting arrangement. This results in minimal relaxation and almost

negligible environmental stress transfer.

VI has eliminated the impact of mass loading by ensuring hermetic integrity and minimizing out-gassing by limiting the number

of internal components through the use of ASIC technology. Mass-loading on the crystal generally results in a frequency decrease

and is typically due to out-gassing of material within a hermetic package or from contamination by external material in a non-

hermetic package. Under normal operating conditions the CD-700 will typically exhibit 2 ppm aging in the rst year of operation.

The device will then typically exhibit 1 ppm aging the following year with a logarithmic decline each year thereafter.

Frequency Divider Feature

The lowest available VCXO OUT1 frequency is 1.000 MHz. To achieve lower frequencies, OUT1 is divided by a 2n counter (n = 1 to

8) and is the OUT2 frequency. The divider values (2, 4, 8, 16, 32, 64, 128 and 256) are set at the factory, so it is user selectable upon

ordering only. In addition, a disabled OUT2 option is also available. To achieve 1.024 MHz, a CD-700 with OUT1 frequency equal

to 16.384 MHz and a divider value equal to 16 would be used. Additional external divider circuits can be used to further lower or

change the frequency.

Loop Filter

A PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input frequency. While

there will be some phase error, theory states there is no frequency error. The loop lter design will dictate many key parameters

such as jitter reduction, stability, lock range and acquisition time. Be advised that many textbook equations describing loop

dynamics, such as capture range are based on ideal systems. Such equations may not be accurate for real systems due to

nonlinearities, DC o sets, noise and do not take into account the limited VCXO bandwidth. This section deals with some real world

design examples. Also, there is loop lter software on the Vectron web site, plus a full sta of experienced applications engineers

who are eager to assist in this process. Common CD-700 PLL applications are shown in Figures 8, 9 (frequency translation), Figure

10 (clock recovery) and Figure 11 (clock smoothing).

Page 5 of 12

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