PD- 94417A
IRFPS30N60K
SMPS MOSFET
Applications
l
Switch Mode Power Supply (SMPS)
l
Uninterruptible Power Supply
l
High Speed Power Switching
Benefits
l
Low Gate Charge Qg results in Simple
Drive Requirement
l
Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l
Fully Characterized Capacitance and
Avalanche Voltage and Current
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case )
HEXFET
®
Power MOSFET
V
DSS
600V
R
DS(on)
typ.
160mΩ
I
D
30A
Super-247™
Max.
30
19
120
450
3.6
± 30
13
-55 to + 150
300
Units
A
W
W/°C
V
V/ns
°C
Avalanche Characteristics
Symbol
E
AS
I
AR
E
AR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Typ.
–––
–––
–––
Max.
520
30
45
Units
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θCS
R
θJA
Parameter
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Typ.
–––
0.24
–––
Max.
0.28
–––
40
Units
°C/W
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1
8/26/04
IRFPS30N60K
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min.
600
–––
–––
3.0
–––
–––
–––
–––
Typ.
–––
0.66
160
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 1mA
190
mΩ V
GS
= 10V, I
D
= 18A
5.0
V
V
DS
= V
GS
, I
D
= 250µA
50
V
DS
= 600V, V
GS
= 0V
µA
250
V
DS
= 480V, V
GS
= 0V, T
J
= 125°C
100
V
GS
= 30V
nA
-100
V
GS
= -30V
Max. Units
Conditions
–––
S
V
DS
= 50V, I
D
= 18A
220
I
D
= 30A
64
nC
V
DS
= 480V
110
V
GS
= 10V
–––
V
DD
= 300V
–––
I
D
= 30A
ns
–––
R
G
= 3.9
Ω
–––
V
GS
= 10V
–––
V
GS
= 0V
–––
V
DS
= 25V
–––
pF
ƒ = 1.0MHz
–––
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
–––
V
GS
= 0V, V
DS
= 480V, ƒ = 1.0MHz
–––
V
GS
= 0V, V
DS
= 0V to 480V
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
oss
eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
16
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
29
120
56
50
5870
530
54
6920
140
270
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Reverse RecoveryCurrent
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
–––
30
A
120
––– ––– 1.5
V
––– 640 960
ns
––– 11
16
µC
––– 31 –––
A
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 30A, V
GS
= 0V
T
J
= 25°C, I
F
= 30A
di/dt = 100A/µs
D
S
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Pulse width
≤
300µs; duty cycle
≤
2%.
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
Starting T
J
= 25°C, L = 1.1mH, R
G
= 25Ω,
I
AS
= 30A
I
SD
≤
30A, di/dt
≤
630A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
150°C
R
θ
is measured at T
J
approximately 90°C
2
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IRFPS30N60K
100
100
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
ID, Drain-to-Source Current (A)
10
ID, Drain-to-Source Current (A)
10
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
TOP
1
5.0V
1
0.1
5.0V
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 150°C
0.1
0.1
1
10
100
0.01
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
100.0
3.0
I
D
= 30A
ID, Drain-to-Source Current
(
A)
T J = 150°C
10.0
R
DS(on)
, Drain-to-Source On Resistance
2.5
2.0
(Normalized)
1.5
1.0
T J = 25°C
1.0
0.1
5.0
6.0
VDS = 50V
20µs PULSE WIDTH
7.0
8.0
9.0
0.5
V
GS
= 10V
0.0
-60
-40
-20
0
20
40
60
80
100
120
140
160
VGS , Gate-to-Source Voltage (V)
T
J
, Junction Temperature
(
°
C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
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3
IRFPS30N60K
1000000
VGS = 0V,
f = 1 MHZ
C iss
= C gs + Cgd ,
SHORTED
Crss = Cgd
Coss = Cds + Cgd
20
C ds
ID= 30A
100000
VGS , Gate-to-Source Voltage (V)
16
VDS= 480V
VDS= 300V
VDS= 120V
C, Capacitance (pF)
10000
Ciss
12
1000
8
Coss
100
4
Crss
10
1
10
100
1000
0
0
40
80
120
160
200
240
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
100.0
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
10.0
TJ = 150°C
10
100µsec
1.0
1msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
1
10
100
10msec
T J = 25°C
0.1
0.2
0.4
0.6
0.8
1.0
VGS = 0V
1.2
1.4
0.1
1000
10000
VSD, Source-toDrain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
4
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IRFPS30N60K
30
V
DS
V
GS
R
D
24
R
G
V
GS
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
D.U.T.
+
-
V
DD
I
D
, Drain Current (A)
18
12
Fig 10a.
Switching Time Test Circuit
6
V
DS
90%
0
25
50
75
100
125
150
T
C
, Case Temperature
( °C)
10%
V
GS
Fig 9.
Maximum Drain Current Vs.
Case Temperature
t
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms
1
(Z
thJC
)
D = 0.50
0.1
0.20
Thermal Response
0.10
0.05
0.02
0.01
P
DM
SINGLE PULSE
(THERMAL RESPONSE)
t
1
t
2
Notes:
1. Duty factor D =
2. Peak T
0.001
0.00001
0.0001
0.001
0.01
t
1
/ t
2
+T
C
1
0.01
J
= P
DM
x Z
thJC
0.1
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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MCU
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