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IXFN75N50

Description
80 A, 500 V, 0.055 ohm, N-CHANNEL, Si, POWER, MOSFET
Categorysemiconductor    Discrete semiconductor   
File Size131KB,4 Pages
ManufacturerIXYS ( Littelfuse )
Websitehttp://www.ixys.com/
Download Datasheet Parametric View All

IXFN75N50 Overview

80 A, 500 V, 0.055 ohm, N-CHANNEL, Si, POWER, MOSFET

IXFN75N50 Parametric

Parameter NameAttribute value
Number of terminals4
Minimum breakdown voltage500 V
Processing package descriptionMINIBLOC-4
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
packaging shapeRectangle
Package SizeFlange mounting
Terminal formUNSPECIFIED
terminal coatingnickel
Terminal locationUPPER
Packaging MaterialsPlastic/Epoxy
structureSingle WITH BUILT-IN diode
Shell connectionisolation
Number of components1
transistor applicationsswitch
Transistor component materialssilicon
Channel typeN channel
field effect transistor technologyMetal-OXIDE SEMICONDUCTOR
operating modeENHANCEMENT
Transistor typeuniversal power supply
Maximum leakage current80 A
Rated avalanche energy6000 mJ
Maximum drain on-resistance0.0550 ohm
Maximum leakage current pulse320 A
HiPerFET
TM
Power MOSFETs
Single Die MOSFET
N-Channel Enhancement Mode
Avalanche Rated, High dv/dt, Low t
rr
V
DSS
IXFN 80N50
IXFN 75N50
D
G
S
I
D25
80 A
75 A
R
DS(on)
50
m
55
m
500 V
500 V
S
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D25
I
DM
I
AR
E
AR
E
AS
dv/dt
P
D
T
J
T
JM
T
stg
V
ISOL
M
d
Weight
Symbol
Test Conditions
T
J
= 25°C to 150°C
T
J
= 25°C to 150°C; R
GS
= 1 MΩ
Continuous
Transient
T
C
= 25°C, Chip capability
T
C
= 25°C, pulse width limited by T
JM
T
C
= 25°C
75N50
80N50
75N50
80N50
Maximum Ratings
500
500
±20
±30
75
80
300
320
80
V
V
V
V
A
A
A
A
A
mJ
J
V/ns
W
°C
°C
°C
V~
V~
miniBLOC, SOT-227 B (IXFN)
E153432
S
G
S
D
G = Gate
S = Source
D = Drain
T
C
= 25°C
T
C
= 25°C
I
S
I
DM
, di/dt
100 A/µs, V
DD
V
DSS
,
T
J
150°C, R
G
= 2
T
C
= 25°C
64
6
5
700
-55 ... +150
150
-55 ... +150
Either Source terminal of miniBLOC can be used
as Main or Kelvin Source
Features
International standard packages
miniBLOC, with Aluminium nitride
isolation
Low R
DS (on)
HDMOS
TM
process
Rugged polysilicon gate cell structure
Unclamped Inductive Switching (UIS)
rated
Low package inductance
50/60 Hz, RMS
I
ISOL
1 mA
t = 1 min
t=1s
2500
3000
Mounting torque
Terminal connection torque
1.5/13 Nm/lb.in.
1.5/13 Nm/lb.in.
30
g
Fast intrinsic Rectifier
Applications
DC-DC converters
Test Conditions
Characteristic Values
(T
J
= 25°C, unless otherwise specified)
min. typ. max.
500
2
4
±200
T
J
= 25°C
T
J
= 125°C
80N50
75N50
100
2
50
55
V
V
nA
µA
mA
mΩ
mΩ
Battery chargers
Switched-mode and resonant-mode
power supplies
DC choppers
Temperature and lighting controls
V
DSS
V
GH(th)
I
GSS
I
DSS
R
DS(on)
V
GS
= 0 V, I
D
= 3 mA
V
DS
= V
GS
, I
D
= 8 mA
V
GS
=
±20
V
DC
, V
DS
= 0
V
DS
= V
DSS
V
GS
= 0 V
V
GS
= 10 V, I
D
= 0.5 I
D25
Pulse test, t
300
µs,
duty cycle d
2 %
Advantages
Easy to mount
Space savings
High power density
© 2002 IXYS All rights reserved
98538C (02/02)

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