M470L3223DT0
256MB DDR SDRAM MODULE
(32Mx64 based on 32Mx 8 DDR SDRAM)
200pin SODIMM
64bit Non-ECC/Parity
Revision 0.0
Dec. 2001
Rev. 0.0 Dec. 2001
M470L3223DT0
Revision History
Revision 0.0 (Dec. 2001)
1. First release.
Rev. 0.0 Dec. 2001
M470L3223DT0
M470L3223DT0 200pin DDR SDRAM SODIMM
32Mx64 200pin DDR SDRAM SODIMM based on 32Mx8
GENERAL DESCRIPTION
The Samsung M470L3223DT0 is 32M bit x 64 Double Data
Rate SDRAM high density memory modules based on third
gen of 256Mb DDR SDRAM respectively.
The Samsung M470L3223DT0 consists of eight CMOS 32M x
8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 200pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M470L3223DT0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
FEATURE
• Performance range
Part No.
Max Freq.
Interface
M470L3223DT0-C(L)B3 166MHz(6ns@CL=2.5)
M470L3223DT0-C(L)A2 133MHz(7.5ns@CL=2)
M470L3223DT0-C(L)B0 133MHz(7.5ns@CL=2.5)
M470L3223DT0-C(L)A0 100MHz(10ns@CL=2)
• Power supply : Vdd: 2.5V
±
0.2V, Vddq: 2.5V
±
0.2V
SSTL_2
•
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB :
Height 1250 (mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
Front
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
Key
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
Pin
Front
Pin
Front
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
Back
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
Key
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
Pin
Back
Pin
Back
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
DQ34
DQ27 135
67
VSS
137
VDD
69
DQ35
139
CB0
71
DQ40
141
CB1
73
VDD
143
VSS
75
DQ41
DQS8 145
77
DQS5
147
CB2
79
VSS
149
VDD
81
DQ42
151
CB3
83
DQ43
153
DU
85
VDD
155
VSS
87
VDD
157
CK2
89
VSS
159
/CK2
91
VSS
161
VDD
93
DQ48
CKE1 163
95
DQ49
97 DU(A13) 165
VDD
167
A12
99
DQS6
169
A9
101
DQ50
171
VSS
103
VSS
173
A7
105
DQ51
175
A5
107
DQ56
177
A3
109
VDD
179
A1
111
DQ57
181
VDD
113
DQS7
115 A10/AP 183
VSS
185
BA0
117
DQ58
187
/WE
119
DQ59
189
/S0
121
VDD
191
DU
123
SDA
193
VSS
125
SCL
127 DQ32 195
129 DQ33 197 VDDSPD
199 VDDID
VDD
131
133 DQS4
136
DQ31
68
138
VDD
70
140
CB4
72
142
CB5
74
144
VSS
76
146
DM8
78
148
CB6
80
150
VDD
82
152
CB7
84
86 DU/(RESET) 154
156
VSS
88
158
VSS
90
160
VDD
92
162
VDD
94
164
CKE0
96
166
DU(BA2)
98
168
A11
100
170
A8
102
172
VSS
104
174
A6
106
176
A4
108
178
A2
110
180
A0
112
182
VDD
114
184
BA1
116
186
/RAS
118
188
/CAS
120
190
/S1
122
192
DU
124
194
VSS
126
196
DQ36
128
198
DQ37
130
200
VDD
132
DM4
134
PIN DESCRIPTION
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0~ CK2,
CK0~ CK2
CKE0
CS0
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
*
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply (2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
No connection
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 Dec. 2001
M470L3223DT0
FUNCTIONAL BLOCK DIAGRAM
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D0
D4
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D1
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D2
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
Clock Wiring
D6
Clock
Input
CK0/CK0
CK1/CK1
CK2/CK2
SDRAMs
4 SDRAMs
4 SDRAMs
NC
Serial PD
SCL
WP
SDA
A0
SA0
A1
SA1
A2
SA2
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D3
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D7
Dram1
±
CK
CK
R=120
Ω
5%
Dram2
Dram3
Dram4
Card
Edge
*Clock Net Wiring
BA0 - BA1
A0 - A13
RAS
CAS
CKE0
WE
BA0-BA1: DDR SDRAMs D0 - D7
V
DDSPD
SPD
D0 - D7
D0 - D7
A0-A13: DDR SDRAMs D0 - D7 V
DD
/V
DDQ
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
VREF
V
SS
V
DDID
D0 - D7
D0 - D7
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD
≠
VDDQ.
Rev. 0.0 Dec. 2001
M470L3223DT0
Absolute Maximum Rate
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
& V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
12
50
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70°C)
Parameter
Supply voltage(for device with a nominal V
DD
of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
+ 0.84V
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
- 0.84V
Output High Current(Half strengh driver)
;V
OUT
= V
TT
+ 0.45V
Output High Current(Half strengh driver)
;V
OUT
= V
TT
- 0.45V
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
V
IX
(DC)
I
I
I
OZ
I
OH
I
OL
I
OH
I
OL
Min
2.3
2.3
VDDQ/2-50mV
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
9
Max
2.7
2.7
VDDQ/2+50mV
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.15
V
DDQ
+0.3
V
DDQ
+0.6
1.35
2
5
Unit
Note
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
mA
3
5
1
2
4
4
Notes
1. Includes
±
25mV margin for DC offset on V
REF
, and a combined total of
±
50mV margin for all AC noise and DC offset on V
REF
,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled
TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of
≤
3nH.
2.V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.0 Dec. 2001
京公网安备 11010802033920号
EEWORLD
