PI49FCT32802
PI49FCT32803
1:5/1:7 3.3V CMOS Clock Drivers
Features
•
•
•
•
•
•
•
•
•
•
Low skew: < 200ps
Fast switching frequency >133 MHz
Fast output rise/fall time < 1.5ns
Low propagation delay < 2.5ns
Low input capacitance < 6.0pF
5V Tolerant input
Rail-to-Rail CMOS outputs
Industrial Temperature: –40°C to +85°C
3.3V ±10% operation
Packages (Pb-free & Green available):
– 16-pin 150-mil wide QSOP (Q)
– 16-pin 173-mil wide TSSOP (L)
Description
Pericom Semiconductor’s PI49FCT3280x is a 3.3V very low-skew
clock buffer from a single low-capacitance input that produces five
outputs on PI49FCT32802 and seven outputs on PI49FCT32803.
Excellent output signals to power and ground ratio minimize power
and ground noise, and also improves output performance.
The PI49FCT3280x integrates series damping resistors on all
outputs.
Pin Configuration (PI49FCT32802)
A
GND
B0
1
2
3
4
5
6
16
15
14
VCC
B4
B3
GND
B2
VCC
Block Diagram (PI49FCT32802)
B
0
B
1
VCC
B1
GND
16-Pin
L, Q
13
12
11
NC
VCC
7
8
10
9
NC
GND
A
B
2
B
3
B
4
Pin Configuration (PI49FCT32803)
A
GND
B0
1
2
3
4
5
6
7
8
16
15
14
VCC
B6
B5
GND
B4
VCC
B3
GND
Block Diagram (PI49FCT32803)
B
0
B
1
VCC
B1
GND
B2
VCC
16-Pin
L, Q
13
12
11
10
9
A
B
2
B
3
Pin Description
Pin Name
PI49FCT32802
PI49FCT32803
A
B0–B6
GND
V
CC
A
B0–B4
GND
V
CC
Description
Input
Outputs
Ground
Power
B
6
1
PS8704A
9/22/04
PI49FCT32802
PI49FCT32803
1:5/1:7 3.3V CMOS Clock Drivers
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................ –65°C to +150°C
Ambient Temperature with Power Applied ........................... –40°C to +85°C
Supply Voltage to Ground Potential........................................ –0.5V to +5.5V
DC Input Voltage .................................................................... –0.5V to +5.5V
DC Output Current............................................................................... 120mA
Power Dissipation ................................................................................... 0.5W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
V
IK
I
OH
I
OL
I
OS
V
H
R
S
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input HIGH current
Input LOW current
Clamp diode voltage
Output HIGH current
Output LOW current
Input Hysteresis
Series Resistor
V
CC
=3V,V
IN
=V
IH
or V
IL
V
CC
=3V, V
IN
=V
IH
or V
IL
Test Conditions
(1)
I
OH
= –8mA
I
OL
= 12mA
Min.
2.4
–
2
–0.5
–
–
–
–25
25
–50
–
Typ.
3
0.4
–
–
–
–
–0.7
–45
45
–100
150
22
Max.
–
0.5
5.5
0.8
1
–1
–1.2
–80
90
–180
–
Units
Guaranteed Logic HIGH Level (Input Pins)
Guaranteed Logic LOW Level (Input Pins)
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= Min., I
IN
= –18mA
V
IN
= 3.6V
V
IN
= 0V
V
µA
V
mA
mV
Ω
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(5)
Short circuit current
(5)
V
CC
= Max., V
OUT
= GND
(5)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(5)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient and maximum loading.
3.
V
OH
= V
CC
– 0.6V
at rated current.
4. This parameter is determined by device characterization but is not production tested.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
2
PS8704A
9/22/04
PI49FCT32802
PI49FCT32803
1:5/1:7 3.3V CMOS Clock Drivers
Power Supply Characteristics
Parameters
I
CC
ΔI
CC
Description
Quiescent Power
Supply Current
Supply Current per
Inputs @ TTL HIGH
Supply Current per
Input per MHz
(4)
V
CC
=
Max.
V
CC
= Max.
V
CC
= Max.,
Outputs Open
Per Output Toggling
50% Duty Cycle
Test Conditions
(1)
V
IN
= GND
or
V
CC
V
IN
= V
CC
–
0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
—
—
—
0.08
0.16
Typ
(2)
0.1
47
Max.
30
µA
300
mA/
MHz
Units
I
CCD
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input (V
IN
=
V
CC
– 0.6V);
all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the
I
C
formula. These limits are guaranteed but not tested.
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
3.0
Max.
4
6
Units
pF
C
IN
C
OUT
Notes:
1. This parameter is determined by device characterization but is not production tested.
Maximum Switching Characteristics
(Over operating range)
Symbol
t
PLH
t
PHL
t
R/tF
t
SK(p)
t
SK(o)
t
SK(t)
F
IN
Description
Propagation Delay A to Bn
(3)
Rise/Fall Time
(2)
Pulse Skew (same pkg)
(1,2)
Output Skew (same pkg.)
(1,2)
Output Skew (different pkg.)
(1,2)
Input Frequency
(1,2)
CL =15pF
Condition
CL =15pF
0.8V –2.0V
Max.
2.5
1.5
0.35
0.2
0.55
133
MHz
ns
Units
Notes:
1. Other loading condition is described on page 4, “Test Circuits for All Outputs.”
2. These parameters are guaranteed by design.
3. Minimum propagation delay of 1.5ns is guaranteed by design.
3
PS8704A
9/22/04
PI49FCT32802
PI49FCT32803
1:5/1:7 3.3V CMOS Clock Drivers
Switching Waveforms
Propagation Delay
3V
Input
t
PLH
Output
t
R
Pulse Skew – t
SK
(p)
3V
Input
t
PLH
Output
t
PHL
1.5V
t
PHL
1.5V
0V
V
OH
1.5V
V
OL
t
SK(p)
=
t
PHL
– t
PLH
0V
V
OH
1.5V
V
OL
2.0V
0.5V
t
F
Output Skew – t
SK
(o)
3V
Input
t
PLHx
Package Skew – t
SK
(t)
1.5V
3V
Input
t
PLH1
Package 1
Output
t
SK(t)
Package 2
Output
t
PLH2
t
PHL2
t
PHLx
0V
1.5V
t
PHL1
V
OH
0V
V
OH
1.5V
t
SK(t)
Ox
1.5V
t
SK(o)
t
SK(o)
V
OL
V
OL
V
OH
1.5V
V
OL
V
OH
Oy
1.5V
t
PLHy
t
PHLy
V
OL
t
SK(o)
=
t
PLHy
– t
PLHx
or
t
PHLy
– t
PHLx
t
SK(t)
=
t
PLH2
– t
PLH1
or
t
PHL2
– t
PHL1
Tests Circuits for All Outputs
V
CC
Pulse
Generator
f = 125MHz
D.U.T.
50Ω
C
L
15pF
4
PS8704A
9/22/04
PI49FCT32802
PI49FCT32803
1:5/1:7 3.3V CMOS Clock Drivers
Packaging Mechanical: 16-pin QSOP (Q)
16
.008
0.20
MIN.
.150
.157
3.81
3.99
.008
.013
0.20
0.33
Guage Plane
.010
0.254
1
.189
.197
4.80
5.00
.008
0.203
REF
Detail A
.016
.035
0.41
0.89
.041
1.04
REF
0˚-6˚
.015 x 45°
0.38
.053
1.35
.069
1.75
SEATING
PLANE
0.41
.016
1.27
.050
Detail A
.007
.010
0.178
0.254
.025
BSC
0.635
.008
.012
0.203
0.305
.004
0.101
.010
0.254
.228
.244
5.79
6.19
X.XX
DENOTES DIMENSIONS IN MILLIMETERS
X.XX
Packaging Mechanical: 16-pin TSSOP (L)
16
.169
.177
4.3
4.5
1
.193
.201
4.9
5.1
.004
.008
0.09
0.20
.047
max.
1.20
SEATING
PLANE
0.45
.018
0.75
.030
.252
BSC
6.4
.0256
BSC
0.65
.007
.012
.002
.006
0.05
0.15
0.19
0.30
X.XX
DENOTES CONTROLLING
X.XX
DIMENSIONS IN MILLIMETERS
5
PS8704A
9/22/04
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