DSC2041
Low-Jitter Configurable Dual HCSL-CMOS Oscillator
General Description
The DSC2041 series of high performance
dual output oscillators utilize a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating additional
device functionality. The two outputs are
controlled by separate supply voltages to
allow for independent voltage level control.
The frequencies of the outputs can be
identical or independently derived from a
common PLL frequency source.
The
DSC2041 has provision for up to eight user-
defined
pre-programmed,
pin-selectable
output frequency combinations.
The
DSC2041 is also equipped with independent
pin-selectable output drive strengths for the
CMOS output to reduce EMI and noise.
DSC2041 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Industrial.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent Outputs
o
HCSL and CMOS
Pin-Selectable Configurations
o
3-bit Output Drive Strength (CMOS)
o
3-bit Output Frequency Combinations
Wide Frequency Range
o
HCSL Output: 2.3 to 460 MHz
o
CMOS Output: 2.3 to 170 MHz
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
_____________________________________________________________________________________________________________________________ _________________
DSC2041
Page 1
MK-Q-B-P-D-12042611-2
DSC2041
Low-Jitter Configurable Dual HCSL-CMOS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
OS0
GND
FS0
FS1
FS2
Output1+
Output1-
OS1
Output 2
VDD2
VDD
OS2
Pin
Type
I
NA
I
Power
I
I
I
O
O
I
O
Power
Power
I
Description
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
Least significant bit for output drive strength selection for CMOS
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive HCSL Output 1
Negative HCSL Output 1
Middle bit for output drive strength selection for CMOS
CMOS output
Power Supply 2 for CMOS Output
Power Supply
Most significant bit for output drive strength selection for CMOS
Operational Description
The DSC2041 is a dual output HCSL-CMOS
oscillator consisting of a MEMS resonator and
a support PLL IC. The two outputs, CMOS and
HCSL, are generated through independent 8-
bit programmable dividers from the output of
the internal PLL. Two constraints are imposed
on the output frequencies: 1) f
2
=M x f
1
/N,
where M and N are even integers between 4
and 254, 2) 1.2GHz < N x f
2
< 1.7GHz.
The actual frequencies output by the DSC2041
are controlled by an internal pre-programmed
memory (OTP).
This memory stores all
coefficients required by the PLL for up to eight
different frequency combinations.
Three
control pins (FS0 – FS2) select the output
frequency combination.
Discera supports
customer defined versions of the DSC2041.
Standard frequency options are described in in
the following sections.
The DSC2041 provides control of the output
voltage levels of the CMOS output. VDD2 (pin
12) sets the high voltage level of Output 2 and
must be equal to or less than VDD at all times
to insure proper operation. VDD2 can be as
low as 1.65V.
When Enable (pin 1) is floated or connected to
VDD, the DSC2041 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The DSC2041 has programmable output drive
strength for CMOS output. Using three control
pins (OS0-OS2), the drive strength for CMOS
output (output 2) can be adjusted to match
circuit board impedances to reduce power
supply noise, overshoot/undershoot and EMI.
Table 1 displays typical rise / fall times for the
output with a 15pf load capacitance as a
function of these control pins at VDD=3.3V
and room temperature.
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OS2, OS1, OS0] - Default [111]
000
001
010
011
100
101
110
111
tr
tf
(ns)
(ns)
2.1
2.5
1.7
2.4
1.6
2.4
1.4
2
1.3
1.8
1.3
1.6
1.2
1.3
1.1
1.3
_____________________________________________________________________________________________________________________________ _________________
DSC2041
Page 2
MK-Q-B-P-D-12042611-2
DSC2041
Low-Jitter Configurable Dual HCSL-CMOS Oscillator
Output Clock Frequencies
Table 2 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code above. Customer defined combinations are available.
Table 2. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
K0001
K000X
Freq
(MHz)
f
OUT1
f
OUT2
f
OUT1
f
OUT2
Freq Select Bits [FS2, FS1, FS0] –
Default is [111]
000
50
25
001
156.25
25
010
200
50
011
200
25
100
125
50
101
125
25
110
100
50
111
100
25
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in
Bold.
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Ordering Code
Condition
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
DSC2041
40sec max.
F I 2
-
xxxxx
T
Freq (MHz)
See Freq. table
Package
F: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Note: 1000+ years of data retention on internal memory
_____________________________________________________________________________________________________________________________ _________________
DSC2041
Page 3
MK-Q-B-P-D-12042611-2
DSC2041
Low-Jitter Configurable Dual HCSL-CMOS Oscillator
(Unless specified otherwise: T=25° C, max CMOS drive strength)
Condition
V
DD
I
DD
I
DD
EN pin low – outputs are disabled
EN pin high – outputs are enabled
HCSL: R
L
=50Ω, F
O1
=125 MHz
CMOS: C
L
=15pF, F
O2
=75 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
0.75xV
DD
-
Specifications
Parameter
Supply Voltage
Supply Current
Supply Current
1
Min.
2.25
Typ.
21
49
Max.
3.6
23
Unit
V
mA
mA
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
±10
±25
±50
±5
5
-
0.25xV
DD
5
20
ppm
ppm
ms
V
ns
ns
kΩ
Pull-up exists on all digital IO
40
HCSL Output
V
OH
V
OL
R
L
=50Ω
Single-Ended
t
R
t
F
f
0
SYM
J
PER
J
CC
20% to 80%
R
L
=50Ω, C
L
= 2pF (to GND)
Single Frequency
Differential
F
O1
=100 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
200
2.3
48
2.5
0.25
0.37
1.7
0.725
-
750
400
460
52
-
0.1
V
mV
ps
MHz
%
ps
RMS
ps
RMS
2
CMOS Output
Output Logic Levels
Output logic high
Output logic low
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Notes:
1.
2.
3.
4.
5.
V
OH
V
OL
t
R
t
F
f
0
SYM
J
PER
J
CC
I=±6mA
20% to 80%
C
L
=15pf
Commercial/Industrial temp range
F
O2
=125 MHz
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.9xV
DD
-
1.1
1.3
2.3
45
3
0.3
0.38
1.7
-
0.1xV
DD
2
2
170
55
V
ns
MHz
%
ps
RMS
ps
RMS
2
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
_____________________________________________________________________________________________________________________________ _________________
DSC2041
Page 4
MK-Q-B-P-D-12042611-2
DSC2041
Low-Jitter Configurable Dual HCSL-CMOS Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
2.5
50MHz-HCSL
Phase Jitter (ps RMS)
156MHz-HCSL
1.5
25MHz-CMOS
Phase Jitter (ps RMS)
2.0
2.0
106MHz-HCSL
212MHz-HCSL
50MHz-CMOS
106MHz-CMOS
125MHz-CMOS
1.5
1.0
1.0
0.5
0.5
0.0
0
200
400
600
800
1000
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
Low-end of integration BW: x kHz to 20 MHz
HCSL Phase jitter (integrated phase noise)
CMOS Phase jitter (integrated phase noise)
Output Waveform: HCSL
t
R
t
F
Output
Output
80
%
50%
20%
675
mv
830
mV
1/
f
o
t
EN
t
DA
V
IH
Enable
V
IL
Output Waveform: CMOS
t
R
V
OH
t
F
Output
V
OL
1/f
o
t
DA
V
IH
t
EN
Enable
V
IL
_____________________________________________________________________________________________________________________________ _________________
DSC2041
Page 5
MK-Q-B-P-D-12042611-2
京公网安备 11010802033920号
EEWORLD
