Operating Temperature Range ......................... -55°C to +125°C
Storage Temperature Range ............................ -55°C to +125°C
Soldering Temperature (reflow) .......................................+260°C
Lead Temperature (soldering, 10s) ................................. +300°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect device reliability.
Package Thermal Characteristics
(Note 1)
PDIP
Junction-to-Ambient Thermal Resistance (θ
JA
) ........110°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...............40°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Recommended Operating Conditions
PARAMETER
Supply Voltage
SYMBOL
V
DD
(Note 2)
CONDITIONS
MIN
2.7
TYP
5.0
MAX
5.5
UNITS
V
DC Electrical Characteristics
(V
DD
= 2.7V to 5.5V, T
A
= -55°C to +125°C, unless otherwise noted.) (Note 3)
PARAMETER
Thermometer Error
Thermometer Resolution
Low-Level Input Voltage
High-Level Input Voltage
Pulse Width of Spikes That Must
Be Suppressed by the Input Filter
Low-Level Output Voltage (SDA)
Input Current Each I/O Pin
I/O Capacitance
Active Supply Current
Standby Supply Current
C
I/O
Temperature conversion
I
CC
I
STBY
E
2
write (Notes 5, 6)
Communication only
(Notes 5, 6, 7)
1
V
IL
V
IH
t
SP
V
OL1
V
OL2
Fast mode
3mA sink current (Note 2)
6mA sink current (Note 2)
0.4 < V
I/O
< 0.9V
DD
(Note 4)
SYMBOL
T
ERR
CONDITIONS
0°C to +70°C
-55°C to +125°C
12-bit
-0.3
0.7 x V
DD
0
0
0
-1
0.0625
0.3 x V
DD
V
DD
+ 0.3
50
0.4
0.6
+1
10
1250
400
125
3
µA
µA
MIN
TYP
MAX
±0.5
±2.0
UNITS
°C
°C
V
V
ns
V
µA
pF
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2
DS1624
Digital Thermometer and Memory
AC Electrical Characteristics
(V
DD
= 2.7V to 5.5V, T
A
= -55°C to +125°C, unless otherwise noted. All values referred to V
IH
= 0.9V
DD
and V
IL
= 0.1V
DD
.)
PARAMETER
Temperature Conversion Time
EEPROM Write Cycle Time
EEPROM Endurance
EEPROM Data Retention
SLK Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated)
START Condition
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for a Repeated START
Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Input Capacitance
Note 2:
Note 3:
SYMBOL
t
TC
t
WR
N
EEWR
t
EEDR
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
C
B
C
I
5
0°C to +70°C (Note 8)
-20°C to +70°C
T
A
= +25°C
-40°C to +70°C
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 10)
(Note 10)
(Notes 10, 11)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Notes 10, 11,
12)
(Notes 8, 10, 12)
(Notes 8, 10, 12)
(Note 10)
(Note 9)
10k
40k
10
0
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
0.6
4.0
400
300
1000
300
300
0.9
0.9
20k
80k
20
400
100
CONDITIONS
MIN
TYP
MAX
200
50
UNITS
ms
ms
Write
Cycles
Years
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
pF
All voltages are referenced to ground.
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage are guaranteed by design and characterization.
Note 4:
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
DD
is switched off.
Note 5:
I
CC
specified with SDA pin open.
Note 6:
I
CC
specified with V
CC
at 5.0V and SDA, SCL = 5.0V, 0°C to +70°C.
Note 7:
EEPROM inactive, temperature sensor in shutdown mode.
Note 8:
For example, if CB = 300pF, then t
R(MIN)
= t
F(MIN)
= 50ns.
Note 9:
Write occurs between 0°C and +70°C.
Note 10:
See the timing diagram (Figure 2). All timing is referenced to 0.9V
DD
and 0.1V
DD
.
Note 11:
After this period, the first clock pulse is generated.
Note 12:
A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
≥ 250ns must then be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 + 250 = 1250ns
before the SCL line is released.
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3
DS1624
Digital Thermometer and Memory
Timing Diagram
SDA
t
BUF
t
SP
t
LOW
t
R
t
F
t
HD:STA
SCL
t
HD:STA
t
HD:DAT
t
HIGH
t
SU:DAT
t
SU:STA
t
SU:STO
STOP
START
REPEATED
START
NOTE:
THE DS1624 DOES NOT DELAY THE SDA LINE INTERNALLY WITH RESPECT TO SCL FOR ANY LENGTH OF TIME
Typical Performance Curve
DS1624 DIGITAL THERMOMETER AND THERMOSTAT TEMPERATURE READING ERROR
5
4
3
2
ERROR (°C)
1
0
-55
-35
-15
5
-1
25
45
65
85
105
125
TYPICAL
ERROR
LOWER LIMIT
SPECIFICATION
-2
-3
TEMPERATURE (°C)
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4
DS1624
Digital Thermometer and Memory
Pin Configurations
TOP VIEW
SDA
SCL
N.C.
GND
1
2
3
4
Pin Description
PIN
NAME
SDA
SCL
N.C.
GND
A2
A1
A0
V
DD
FUNCTION
Data Input/Output Pin for 2-Wire Serial
Communication Port
Clock Input/Output Pin for 2-Wire Serial
Communication Port
No Connection. No Internal Connection.
Ground
Address Input
Address Input
Address Input
2.7V to 5.5V Input Power-Supply Voltage
1
2
3
4
5
6
7
8
+
DS1624
8
7
6
5
V
DD
A0
A1
A2
SO (208 mils)
1
2
3
4
SDA
SCL
N.C.
DS1624
V
DD
A0
A1
A2
8
7
6
5
GND
PDIP (300 mils)
Detailed Description
2-Wire Serial Data Bus
The DS1624 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data onto
the bus is defined as a transmitter, and a device receiving
data as a receiver. The device that controls the message
is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by
a master device which generates the serial clock (SCL),
controls the bus access, and generates the START and
STOP conditions. The DS1624 operates as a slave on
the two-wire bus. Connections to the bus are made via
the open-drain I/O lines SDA and SCL. The following bus
protocol has been defined (see Figure 2):
●
●
Data transfer can be initiated only when the bus is
not busy.
During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
Accordingly, the following bus conditions have been
defined:
Bus Not Busy:
Both data and clock lines remain high.
Start Data Transfer:
A change in the state of the data
line, from high to low, while the clock is high, defines a
START condition.
Stop Data Transfer:
A change in the state of the data
line, from low to high, while the clock line is high, defines
the STOP condition.
Data Valid:
The state of the data line represents valid
data when, after a START condition, the data line is stable
for the duration of the high period of the clock signal. The
data on the line must be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is not limited, and is determined by the master device.
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