a
FEATURES
10 MHz–300 MHz Input Frequency
6.8 kHz–270 kHz Output Signal Bandwidth
8.1 dB SSB NF
0 dBm IIP3
AGC Free Range up to –34 dBm
12 dB Continuous AGC Range
16 dB Front End Attenuator
Baseband I/Q 16-bit (or 24-bit) Serial Digital Output
LO and Sampling Clock Synthesizers
Programmable Decimation Factor, Output Format,
AGC, and Synthesizer Settings
370 Input Impedance
2.7 V–3.6 V Supply Voltage
Low Current Consumption: 20 mA
48–Lead LQFP Package (1.4 mm Thick)
APPLICATIONS
Multimode Narrowband Radio Products
Analog/Digital UHF/VHF FDMA Receivers
TETRA, APCO25, GSM/EDGE
Portable and Mobile Radio Products
Base Station Applications
IF Digitizing Subsystem
AD9874
*
GENERAL DESCRIPTION
The AD9874 is a general-purpose IF subsystem that digitizes a
low level 10 MHz–300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874
consists of a low noise amplifier, a mixer, a band-pass sigma-delta
analog-to-digital converter, and a decimation filter with program-
mable decimation factor. An automatic gain control (AGC) circuit
gives the AD9874 12 dB of continuous gain adjustment. Auxiliary
blocks include both clock and LO synthesizers.
The AD9874’s high dynamic range and inherent antialiasing
provided by the band-pass sigma-delta converter allow the
AD9874 to cope with blocking signals up to 95 dB stronger
than the desired signal. This attribute can often reduce the cost of
a radio by reducing its IF filtering requirements. Also, it enables
multimode radios of varying channel bandwidths, allowing the
IF filter to be specified for the largest channel bandwidth.
The SPI port programs numerous parameters of the AD9874,
thus allowing the device to be optimized for any given
application. Programmable parameters include the following:
synthesizer divide ratios; AGC attenuation and attack/decay
time; the received signal strength level; decimation factor; the
output data format; 16 dB attenuator; and the selected bias
currents. The bias currents of the LNA and mixer can be further
reduced at the expense of the degraded performance for battery-
powered applications.
FUNCTIONAL BLOCK DIAGRAM
MXOP MXON IF2P IF2N
GCP GCN
DAC
–16dB
AGC
AD9874
IFIN
LNA
- ADC
DECIMATION
FILTER
FORMATTING/SSI
DOUTA
DOUTB
FS
CLKOUT
FREF
CONTROL LOGIC
LO
SYNC
SAMPLE CLOCK
SYNTHESIZER
VOLTAGE
REFERENCE
SPI
IOUTL
LOP LON
LO VCO AND
LOOP FILTER
IOUTC
CLKP
CLKN
VREFP VCM VREFN
PC
PD
PE
SYNCB
LO VCO AND
LOOP FILTER
*Protected
by U.S. Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
=
VDDD = VDDH 2.7 to
AD9874–SPECIFICATIONS
(VDDI f= VDDF = VDDA =f VDDC16.8VDDL =unless otherwise= noted.)3.6 V,
VDDQ = VDDP = 2.7 V to 5.5 V, f = 18 MSPS, f = 109.65 MHz, = 107.4 MHz,
=
MHz,
CLK
IF
LO
REF
1
Parameter
SYSTEM DYNAMIC PERFORMANCE
2
SSB Noise Figure @ Min VGA Attenuation
3,
4
@ Max VGA Attenuation
3, 4
Dynamic Range with AGC Enabled
3, 4
IF Input Clip Point @ Max VGA Attenuation
3
@ Min VGA Attenuation
3
Input Third Order Intercept (IIP3)
Gain Variation over Temperature
LNA + MIXER
Maximum RF and LO Frequency Range
LNA Input Impedance
Mixer LO Input Resistance
LO SYNTHESIZER
LO Input Frequency
LO Input Amplitude
FREF (Reference) Frequency
FREF Input Amplitude
Minimum Charge Pump Current
@
5 V
5
Maximum Charge Pump Current
@
5 V
5
Charge Pump Output Compliance
6
Synthesizer Resolution
CLOCK SYNTHESIZER
CLK Input Frequency
CLK Input Amplitude
Minimum Charge Pump Output Current
5
Maximum Charge Pump Output Current
5
Charge Pump Output Compliance
6
Synthesizer Resolution
SIGMA-DELTA ADC
Resolution
Clock Frequency (f
CLK
)
Center Frequency
Pass-Band Gain Variation
Alias Attenuation
GAIN CONTROL
Programmable Gain Step
AGC Gain Range (Continuous)
OVERALL
Analog Supply Voltage
(VDDA, VDDF, VDDI)
Digital Supply Voltage
(VDDD, VDDC, VDDL)
Interface Supply Voltage
7
(VDDH)
Charge Pump Supply Voltage
(VDDP, VDDQ)
Total Current
High Performance Setting
8
Low Power Mode
8
Standby
OPERATING TEMPERATURE RANGE
Temp
Full
Full
Full
Full
Full
Full
Full
Full
25
o
C
25
o
C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
V
V
IV
IV
IV
IV
VI
VI
VI
IV
IV
IV
VI
VI
VI
IV
IV
IV
V
IV
IV
V
V
Min
Typ
8.1
13
95
–19
–31
0
0.7
500
370//1.4
1
Max
9.5
Unit
dB
dB
dB
dBm
dBm
dBm
dB
MHz
Ω//pF
kΩ
91
–20
–32
–5
2
300
7.75
0.3
0.1
0.3
0.48
3.87
0.4
6.25
13
0.3
0.48
3.87
0.4
2.2
16
13
0.67
5.3
300
2.0
25
3
0.78
6.2
VDDP – 0.4
MHz
V p-p
MHz
V p-p
mA
mA
V
kHz
MHz
V p-p
mA
mA
V
kHz
Bits
MHz
MHz
dB
dB
dB
dB
0.67
5.3
26
V
DDC
0.78
6.2
VDDQ – 0.4
24
26
f
CLK
/8
1.0
80
16
12
Full
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
VI
VI
2.7
2.7
1.8
2.7
3.0
3.0
3.6
3.6
3.6
V
V
V
V
mA
mA
mA
°C
5.0
20
17
0.01
5.5
26.5
22
0.1
+85
–40
NOTES
1
Standard operating mode: LNA/Mixer @ high bias setting, VGA @ Min ATTEN setting, synthesizers in normal (not fast acquire) mode, f
CLK
= 18 MHz, decimation
factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
2
This includes 0.9 dB loss of matching network.
3
AGC with DVGA enabled.
4
Measured in 10 kHz bandwidth.
5
Programmable in 0.67 mA steps.
6
Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
7
VDDH must be less than VDDD + 0.5 V.
8
Clock VCO off, add additional 0.7 mA with VGA @ Max ATTEN setting.
Specifications subject to change without notice.
–2–
REV. 0
AD9874
DIGITAL SPECIFICATIONS
Parameter
DECIMATOR
Decimation Factor
2
Pass-Band Width
Pass-Band Gain Variation
Alias Attenuation
SPI-READ OPERATION (See Figure 1a)
PC Clock Frequency
PC Clock Period (t
CLK
)
PC Clock HI (t
HI
)
PC Clock LOW (t
LOW
)
PC to PD Setup Time (t
DS
)
PC to PD Hold Time (t
DH
)
PE
to PC Setup Time (t
S
)
PC to
PE
Hold Time (t
H
)
SPI-WRITE OPERATION
3
(See Figure 1b)
PC Clock Frequency
PC Clock Period (t
CLK
)
PC Clock HI (t
HI
)
PC Clock LOW (t
LOW
)
PC to PD Setup Time (t
DS
)
PC to PD Hold Time (t
DH
)
PC to PD (or DOUBT) Data Valid Time (t
DV
)
PE
to PD Output Valid to Hi-Z (t
EZ
)
SSI
3
(see Figure 2b)
CLKOUT Frequency
CLKOUT Period (t
CLK
)
CLKOUT Duty Cycle (t
HI,
t
LOW
)
CLKOUT to FS Valid Time (t
V
)
CLKOUT to DOUT Data Valid Time (t
DV
)
CMOS LOGIC INPUTS
4
Logic “1” Voltage (V
IH
)
Logic “0” Voltage (V
IL
)
Logic “1” Current (V
IH
)
Logic “0” Current (V
IL
)
Input Capacitance
CMOS LOGIC OUTPUTS
3,4,5
Logic “1” Voltage (V
IH
)
Logic “0” Voltage (V
IL
)
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V,
f
CLK
= 18 MSPS, f
IF
= 109.65 MHz, f
LO
= 107.4 MHz, f
REF
= 16.8 MHz, unless otherwise noted.)
1
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
48
50%
1.2
88
10
100
45
45
2
2
5
5
10
100
45
45
2
2
3
8
0.867
38.4
33
–1
–1
VDDH–0.2
0.5
10
10
3
VDDH–0.2
0.2
26
1153
67
1
1
Typ
Max
960
f
CLKOUT
dB
dB
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
V
V
mA
mA
pF
V
V
Unit
50
NOTES
1
Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f
CLK
= 18 MHz, decimation factor = 300, 10 pF load on SSI output pins:
VDDx = 3.0 V.
2
Programmable in steps of 48 or 60.
3
CMOS output mode with C
LOAD
= 10 pF and Drive Strength = 7.
4
Absolute Max and Min input/output levels are VDDH +0.3 V and –0.3 V.
5
I
OL
= 1 mA; specification is also dependent on Drive Strength setting.
Specifications subject to change without notice.
REV. 0
–3–
AD9874
ABSOLUTE MAXIMUM RATINGS*
Parameter
VDDF, VDDA, VDDC, VDDD, VDDH,
VDDL, VDDI
VDDF, VDDA, VDDC, VDDD, VDDH,
VDDL, VDDI
VDDP, VDDQ
GNDF, GNDA, GNDC, GNDD, GNDH,
GNDL, GNDI, GNDQ, GNDP, GNDS
MXOP, MXON, LOP, LON, IFIN,
CXIF, CXVL, CXVM
PC, PD, PE, CLKOUT, DOUTA,
DOUTB, FS, SYNCB
IF2N, IF2P, GCP, GCN
VREFP, VREFN, RREF
IOUTC
IOUTL
CLKP, CLKN
FREF
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
With Respect to
GNDF, GNDA, GNDC, GNDD, GNDH,
GNDL, GNDI, GNDS
VDDR, VDDA, VDDC, VDDD, VDDH,
VDDL, VDDI
GNDP, GNDQ
GNDF, GNDA, GNDC, GNDD, GNDH,
GNDL, GNDI, GNDQ, GNDP, GNDS
GNDI
GNDH
GNDF
GNDA
GNDQ
GNDP
GNDC
GNDL
Min
–0.3
–4.0
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
Max
+4.0
+4.0
+6.0
+0.3
VDDI + 0.3
VDDH + 0.3
VDDF + 0.3
VDDA + 0.3
VDDQ + 0.3
VDDP + 0.3
VDDC + 0.3
VDDL + 0.3
150
+150
300
Unit
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
*Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
EXPLANATION OF TEST LEVELS
TEST LEVEL
48-Lead LQFP
θ
JA
= 76.2°C/W
θ
JC
= 17°C/W
I. 100% production tested.
II. 100% production tested at 25
°
C and sample tested at specified
temperatures. AC testing done on sample basis.
III. Sample tested only.
IV. Parameter is guaranteed by design and/or characterization testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at 25°C; min. and max.
guaranteed by design and characterization for industrial
temperature range.
ORDERING GUIDE
Model
Temperature Range
Package Description
48-Lead Thin Plastic Quad Flatpack (LQFP)
Evaluation Board
Package Option
ST-48
AD9874BST –40°C to +85°C
AD9874EB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9874 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD9874
PIN CONFIGURATION
IOUTL
GNDP
36
GNDL
35
FREF
34
GNDS
33
SYNCB
32
GNDH
31
FS
30
DOUTB
29
DOUTA
28
CLKOUT
27
VDDH
26
VDDD
25
PE
13 14 15 16 17 18 19 20 21 22 23 24
CXVM
48 47 46 45 44 43 42 41 40 39 38 37
MXOP
1
MXON
2
GNDF
3
IF2N
4
IF2P
5
VDDF
6
GCP
7
GCN
8
VDDA
9
GNDA
10
VREFP
11
VREFN
12
PIN 1
IDENTIFIER
AD9874
TOP VIEW
(Not to Scale)
VDDQ
IOUTC
GNDQ
VDDC
GNDC
CLKP
CLKN
GNDS
GNDD
VDDP
VDDL
CXVL
GNDI
VDDI
CXIF
LON
LOP
IFIN
PIN FUNCTION DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Mnemonic
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
VREFN
RREF
VDDQ
IOUTC
GNDQ
VDDC
GNDC
CLKP
CLKN
GNDS
GNDD
PC
PD
PE
VDDD
Description
Mixer Output, Positive
Mixer Output, Negative
Ground for Front End of ADC
Second IF Input (to ADC), Negative
Second IF Input (to ADC), Positive
Positive Power Supply for Front End of ADC
Filter Capacitor for ADC Full-Scale Control
Full-Scale Control Ground
Positive Power Supply for ADC Back End
Ground for ADC Back End
Voltage Reference, Positive
Voltage Reference, Negative
Reference Resistor: Requires 100 kΩ to
GNDA
Positive Power Supply for Clock Synthesizer
Clock Synthesizer Charge Pump Output
Current
Ground for Clock Synthesizer Charge
Pump
Positive Power Supply for Clock Synthesizer
Ground for Clock Synthesizer
Sampling Clock Input/Clock VCO Tank,
Positive
Sampling Clock Input/Clock VCO Tank,
Negative
Substrate Ground
Ground for Digital Functions
Clock Input for SPI Port
Data I/O for SPI Port
Enable Input for SPI Port
Positive Power Supply for Internal Digital
Functions
Pin
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Mnemonic
VDDH
CLKOUT
DOUTA
DOUTB
FS
GNDH
SYNCB
GNDS
FREF
GNDL
GNDP
IOUTL
VDDP
VDDL
CXVM
LON
LOP
CXVL
GNDI
CXIF
IFIN
VDDI
Description
Positive Power Supply for Digital Interface
Clock Output for SSI Port
Data Output for SSI Port
Data Output for SSI Port (Inverted) or
SPI Port
Frame Sync for SSI Port
Ground for Digital Interface
Resets SSI and Decimator Counters;
Active Low
Substrate Ground
Reference Frequency Input for Both
Synthesizers
Ground for LO Synthesizer
Ground for LO Synthesizer Charge Pump
LO Synthesizer Charge Pump Output
Current Charge Pump
Positive Power Supply for LO Synthesizer
Charge Pump
Positive Power Supply for LO Synthesizer
External Filter Capacitor; DC Output of LNA
LO Input to Mixer and LO Synthesizer,
Negative
LO Input to Mixer and LO Synthesizer,
Positive
External Bypass Capacitor for LNA Power
Supply
Ground for Mixer and LNA
External Capacitor for Mixer V-I Converter
Bias
First IF Input (to LNA)
Positive Power Supply for LNA and Mixer
REV. 0
RREF
–5–
PC
PD
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