MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTP4N50E/D
™
Data Sheet
TMOS E-FET.
™
High Energy Power FET
Designer's
MTP4N50E
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
This advanced high voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
•
Avalanche Energy Capability Specified at Elevated
Temperature
•
Low Stored Gate Charge for Efficient Switching
•
Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode
•
Source–to–Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode
D
TMOS POWER FET
4.0 AMPERES
500 VOLTS
RDS(on) = 1.5 OHMS
®
G
S
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage
— Non–repetitive
Drain Current — Continuous
Drain Current
— Pulsed
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage Temperature Range
Symbol
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
TJ, Tstg
Value
500
500
±
20
±
40
4.0
10
75
0.6
– 55 to 150
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Watts
W/°C
°C
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS
(TJ < 150°C)
Single Pulse Drain–to–Source Avalanche Energy — TJ = 25°C
Single Pulse Drain–to–Source Avalanche Energy
— TJ = 100°C
Repetitive Pulse Drain–to–Source Avalanche Energy
WDSR (1)
WDSR (2)
280
44
7.4
mJ
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) VDD = 50 V, ID = 4.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
R
θJC
R
θJA
TL
1.67
62.5
260
°C/W
°C
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 1
©
Motorola TMOS
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
MTP4N50E
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0, ID = 250
µAdc)
Zero Gate Voltage Drain Current
(VDS = 500 V, VGS = 0)
(VDS = 400 V, VGS = 0, TJ = 125°C)
Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)
Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
(TJ = 125°C)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 2.0 A)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 4.0 Adc)
(ID = 2.0 A, TJ = 100°C)
Forward Transconductance (VDS = 15 Vdc, ID = 2.0 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS*
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
Forward Turn–On Time
Reverse Recovery Time
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
* Indicates Pulse Test: Pulse Width = 300
µs
Max, Duty Cycle
≤
2.0%.
** Limited by circuit inductance.
Ld
—
—
Ls
—
3.5
4.5
7.5
—
—
—
nH
(IS = 4.0 A, di/dt = 100 A/µs)
VSD
ton
trr
—
—
—
—
**
—
1.4
—
760
Vdc
ns
(VDS = 400 V, ID = 4.0 A,
VGS = 10 V)
(VDD = 250 V, ID
≈
4.0 A,
RG = 12
Ω,
RL = 62
Ω,
VGS(on) = 10 V)
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
—
—
—
—
—
—
—
24
34
60
36
27
3.5
14
—
—
—
—
32
—
—
nC
ns
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
Ciss
Coss
Crss
—
—
—
775
84
19
—
—
—
pF
VGS(th)
2.0
1.5
RDS(on)
VDS(on)
—
—
gFS
1.5
—
—
—
7.5
6.0
—
mhos
—
—
—
1.3
4.0
3.5
1.5
Ohm
Vdc
Vdc
V(BR)DSS
IDSS
—
—
IGSSF
IGSSR
—
—
—
—
—
—
0.25
1.0
100
100
nAdc
nAdc
500
—
—
Vdc
mAdc
Symbol
Min
Typ
Max
Unit
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP4N50E
TYPICAL ELECTRICAL CHARACTERISTICS
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
8
TJ = 25°C
I D, DRAIN CURRENT (AMPS)
6
1.2
VDS = VGS
ID = 0.25 mA
VGS = 10 V
8V
7V
1.1
1
4
6V
0.9
2
5V
4V
0.8
0
0
8
12
16
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
4
20
–50
–25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
Figure 1. On–Region Characteristics
Figure 2. Gate–To–Source Threshold Voltage
Variation With Temperature
VBR(DSS), DRAIN–TO–SOURCE BREAKDOWN
VOLTAGE (NORMALIZED)
8
VDS
≥
10 V
I D, DRAIN CURRENT (AMPS)
6
1.2
VGS = 0
ID = 0.25 mA
1.1
4
1
0.9
2
TJ = 100°C
–55°C
0
0
4
6
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
2
10
25°C
0.8
–50
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Transfer Characteristics
Figure 4. Breakdown Voltage Variation
With Temperature
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
VGS = 10 V
2.4
2
1.6
25°C
1.2
0.8
0.4
0
0
2
4
6
8
10
ID, DRAIN CURRENT (AMPS)
–55°C
TJ = 100°C
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2.8
2.5
VGS = 10 V
ID = 2 A
2
1.5
1
0.5
0
–50
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance versus Drain Current
Figure 6. On–Resistance Variation
With Temperature
Motorola TMOS Power MOSFET Transistor Device Data
3
MTP4N50E
SAFE OPERATING AREA INFORMATION
10
I D, DRAIN CURRENT (AMPS)
0.1 ms
10
µs
I D, DRAIN CURRENT (AMPS)
14
12
10
8
6
4
2
0
1
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
0
100
200
300
400
500
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
600
TJ
≤
150°C
1
VGS = 20 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1 ms
10 ms
dc
0.1
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maxi-
mum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 8 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.
1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.5
0.3
0.2
0.1
0.1
0.05
0.05
0.03
0.02
0.01
0.1
0.2
0.5
1
2
5
t, TIME (ms)
0.02
P(pk)
D = 0.5
0.2
Figure 8. Maximum Rated Switching
Safe Operating Area
The power averaged over a complete switching cycle must
be less than:
TJ(max) – TC
R
θJC
10000
VDD = 250 V
ID = 4 A
VGS = 10 V
TJ = 25°C
td(off)
tf
tr
td(on)
1000
t, TIME (ns)
100
10
1
10
100
RG, GATE RESISTANCE (OHMS)
1000
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
SINGLE PULSE
0.01
0.01
0.02
0.05
t2
DUTY CYCLE, D = t1/t2
10
20
t1
R
θJC
(t) = r(t) R
θJC
R
θJC
= 1.67°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) R
θJC
(t)
50
100
200
500
1000
Figure 10. Thermal Response
4
Motorola TMOS Power MOSFET Transistor Device Data
MTP4N50E
2000
VGS, GATE SOURCE VOLTAGE (VOLTS)
TJ = 25°C
VGS = 0
1500
C, CAPACITANCE (pF)
16
TJ = 25°C
ID = 4 A
12
400 V
8
VDS = 100 V
250 V
1000
Crss
500
VDS = 0
0
Ciss
4
Coss
5
5
10
20
25
15
0
VGS
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
10
0
0
10
20
30
QG, TOTAL GATE CHARGE (nC)
40
50
Figure 11. Capacitance Variation
Figure 12. Gate Charge versus
Gate–To–Source Voltage
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of
Figure 14 defines the limits of safe operation for commutated
source–drain current versus re–applied drain voltage when
the source–drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when wave-
forms similar to those of Figure 13 are present. Full or half–
bridge PWM DC motor controllers are common applications
requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by de-
vice, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum for-
ward source–drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
6
RGS
I D, DRAIN CURRENT (AMPS)
DUT
Stray inductances in Motorola’s test circuit are assumed to
be practical minimums. dVDS/dt in excess of 10 V/ns was at-
tained with dIs/dt of 400 A/µs.
15 V
VGS
0
IFM
90%
IS
10%
ton
IRM
0.25 IRM
VDS(pk)
VR
VDS
dVDS/dt
VdsL
MAX. CSOA
STRESS AREA
dls/dt
trr
Vf
Figure 15. Commutating Waveforms
4
–
VR
IFM
+
20 V
–
IS
VDS
Li
2
di/dt
≤
75 A/µs
+
VGS
0
0
500
100
200
300
400
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
600
VR = 80% OF RATED VDS
VdsL = Vf + Li
⋅
dls/dt
Figure 13. Commutating Safe Operating Area (CSOA)
Figure 14. Commutating Safe Operating Area
Test Circuit
5
Motorola TMOS Power MOSFET Transistor Device Data
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