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PI74LPT244AQE

Description
Buffers u0026 Line Drivers Octal Buffer Line Driver
Categorylogic    logic   
File Size438KB,12 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Environmental Compliance
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PI74LPT244AQE Overview

Buffers u0026 Line Drivers Octal Buffer Line Driver

PI74LPT244AQE Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerPericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging codeQSOP
package instructionSSOP, SSOP20,.25
Contacts20
Reach Compliance Codecompliant
ECCN codeEAR99
Control typeENABLE LOW
seriesLPT
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length8.65 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits4
Number of functions2
Number of ports2
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP20,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3/3.3 V
Prop。Delay @ Nom-Sup4.8 ns
propagation delay (tpd)4.8 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width3.9 mm
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV3810/PI90LVR3810
High-Speed Differential
Line Receivers
Features
• Ten line receivers meet or exceed the requirements of the
ANSI TIA/EIA-644-1995 Standard
• Designed for signaling rates up to 660 Mbps
• 0V to 3V common-mode input voltage range
• Operates from a single 3.3V supply
• Typical propagation delay time: 2.6ns
• Output skew 100ps (typical)
• Part-to-part skew is less than 1ns
• PI90LVR3810
Set up time: typical 1ns
Max. clock to output: 1ns
• Integrated 110-ohm termination on PI90LVT386
• Low Voltage TTL (LVTTL) levels are 5V tolerant
• Open-circuit fail safe
• Flow-through pin out
• Packaging:
48-Pin Thin Shrink Small Output TSSOP (A)
Description
The PI90LVx3810 family consists of ten differential line receivers
with 3-state outputs that implement Low-Voltage Differential Sig-
naling (LVDS). The PI90LVR3810 has integrated edge-triggered
D-type flops. Any of the differential receivers will provide a valid
logical output state with a ±100mV differential input voltage within
the input common-mode voltage range that allows 0 to 3V of ground
potential difference between two LVDS nodes. The independent EN
pins can be used to place the outputs in either a normal logic state
(high or low logic levels) or a high-impedance state. In high-
impedance state, outputs neither load nor drive the bus lines.
The intended application of these devices, and their signaling
techniques, is for point-to-point baseband data transmission over
controlled impedance media of approximately 100-Ohms with a 100-
Ohm termination resistor. The transmission media may be printed
circuit board traces, backplanes, or cables. The PI90LV3810’s 10
receivers integrated into the same substrate allow precise timing
alignment. In addition, the PI90LVR3810's integrated registers
resynchronize the data to the system clock, for additional signal
deskew.
The integrated registers in the PI90LVR3810 are particularly suitable
for interfacing with LVDS drivers such as the PI90LV3811 over long
distances where signal-to-signal skew may be a problem. On the
positive transition of the differential clock (CLK±) input, the Q
outputs of the flip-flop take on the logic levels set up at the
differential data (RIN±) inputs.
Old data can be retained or new data can be entered while the
outputs are in the high-impedance state. The EN pins do not affect
the internal operation of the flip-flops.
PI90LV3810
PI90LVR3810 Truth Table
SET
0
1
R
OUT
Q=D
Q=1
1
PS8664
02/21/03

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Product Category - - Buffers & Line Drivers Buffers & Line Drivers Buffers & Line Drivers Buffers & Line Drivers
Manufacturer - - Pericom Semiconductor Corporation (Diodes Incorporated) Pericom Semiconductor Corporation (Diodes Incorporated) Pericom Semiconductor Corporation (Diodes Incorporated) Pericom Semiconductor Corporation (Diodes Incorporated)
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