DATASHEET
LOW SKEW CLOCK INVERTER AND DIVIDER
Description
The ICS548A-03 is a low cost, low skew, high-performance
general purpose clock designed to produce a set of one
output clock, one inverted output clock, and one clock
divided-by-two. Using our patented Phase-Locked Loop
(PLL) techniques, the device operates from a frequency
range of 10 MHz to 120 MHz in the PLL mode, and up to
160 MHz in the non-PLL mode.
In applications that need to maintain low phase noise in the
clock tree, the non-PLL (when S3=S2=1) modes should be
used.
This chip is not a zero delay buffer. Many applications may
be able to use the ICS527 for zero delay dividers.
ICS548A-03
Features
•
•
•
•
•
•
Packaged in 16-pin SOIC (150 mil)
Input clock up to 160 MHz in the non-PLL mode
Provides clock outputs of CLK, CLK, and CLK/2
Low skew (500 ps) on CLK, CLK, and CLK/2
All outputs can be tri-stated
Entire chip can be powered down by changing one or two
select pins
•
3.3 V operating range
•
Available in commercial and industrial temperature
ranges
•
RoHS 5 (green) or RoHS 6 (green and lead free)
compliant package
Block Diagram
VDD
GND
2
2
CLK
S3:S0
4
Clock
input
Input
Buffer
Clock
Synthesis
and Divider
Circuitry
CLK
CLK/2
OE (all outputs)
IDT™ / ICS™
LOW SKEW CLOCK INVERTER AND DIVIDER
1
ICS548A-03
REV C 063006
ICS548A-03
LOW SKEW CLOCK INVERTER AND DIVIDER
CLOCK DIVIDER
Pin Assignment
ICLK
VDD
VDD
S3
GND
GND
S2
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DC
DC
DC
CLK
CLK
CLK/2
OE
S1
CLK, CLK, and CLK/2 Select Table (MHz)
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK, CLK
Low
Input/4
Input
Input/2
Low
Input x 2
Input/5
Input/3
Low
Input/4
Input
Input/2
Low
Input/6
Input/8
Input/2
CLK/2
Low
Input/8
Input/2
Input/4
Low
Input
Input/10
Input/6
Low
Input/8
Input/2
Input/4
Low
Input/12
Input/16
Input/4
PLL
OFF
ON
ON
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
Input Range
Power Down
30 - 120
20 - 40
20 - 80
Power Down
10 - 20
40 - 120
25 - 120
Power Down
30 - 120
20 - 40
20 - 80
Power Down
0 - 160
0 - 160
0 - 80
IDT™ / ICS™
LOW SKEW CLOCK INVERTER AND DIVIDER
2
ICS548A-03
REV C 063006
ICS548A-03
LOW SKEW CLOCK INVERTER AND DIVIDER
CLOCK DIVIDER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
ICLK
VDD
VDD
S3
GND
GND
S2
S0
S1
OE
CLK/2
CLK
CLK
DC
DC
DC
Pin
Type
Input
Power
Power
Input
Power
Power
Input
Input
Input
Input
Clock input.
Connect to 3.3 V.
Connect to 3.3 V.
Pin Description
Clock Select 3. See table on page 2.
Connect to ground.
Connect to ground.
Clock Select 2. See table on page 2.
Clock Select 0. See table on page 2.
Clock Select 1. See table on page 2.
Output Enable. Tri-states all clock outputs when low.
Output Clock output divided by 2. See table on page 2.
Output Clock output. See table on page 2.
Output Inverted clock output. See table on page 2.
—
—
—
Don’t connect. Do not connect anything to this pin.
Don’t connect. Do not connect anything to this pin.
Don’t connect. Do not connect anything to this pin.
External Components
The ICS548A-03 requires a minimum number of external components for proper operation. Decoupling capacitors
of 0.01µF should be connected between pins 3 and 5, as close to the device as possible. Connect pin 2 directly to
pin 3, and pin 6 directly to pin 5. A series termination resistor of 33Ω should be used on all clock outputs, as close
to the device as possible. Leave any unused clock outputs floating. There are no pull-up resistors on the input pins,
and they may be connected directly to VDD or ground.
IDT™ / ICS™
LOW SKEW CLOCK INVERTER AND DIVIDER
3
ICS548A-03
REV C 063006
ICS548A-03
LOW SKEW CLOCK INVERTER AND DIVIDER
CLOCK DIVIDER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS548A-03. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referenced to GND)
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
-0.5 V to 7 V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+3.13
Typ.
Max.
+70
+85
+3.47
Units
°
C
°
C
V
DC Electrical Characteristics
VDD = 3.3 V,
Ambient temperature -40° C to +85° C , unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage,
CMOS level
Output High Voltage
Output Low Voltage
Operating Supply
Current, 100 MHz clock
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
IDD
I
OS
C
IN
Conditions
ICLK only (pin 1)
ICLK only (pin 1)
All other inputs
All other inputs
I
OH
= -8 mA
I
OH
= -12 mA
I
OL
= 12 mA
S3=S2=S0=0, S1=1
Each output
All inputs
Min.
3.13
(VDD/2)+1
2
Typ.
VDD/2
VDD/2
Max.
3.47
(VDD/2)-1
0.8
Units
V
V
V
V
V
V
V
VDD-0.4
2.4
0.4
20
±50
5
V
mA
mA
pF
IDT™ / ICS™
LOW SKEW CLOCK INVERTER AND DIVIDER
4
ICS548A-03
REV C 063006
ICS548A-03
LOW SKEW CLOCK INVERTER AND DIVIDER
CLOCK DIVIDER
AC Electrical Characteristics
VDD = 3.3 V,
Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Input Frequency, clock
input, PLL on
Input Frequency, clock
input, PLL off
Output Frequency (see
table on page 2)
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Output Enable Time, OE
high to output on
Output Disable Time, OE
to tri-state
Absolute Clock Period
Jitter. PLL modes
One Sigma Clock Period
Jitter, PLL modes
Output clock skew for
CLK, CLK, or CLK/2
Symbol
f
IN
f
IN
f
OUT
t
OR
t
OF
t
DC
Conditions
Min.
10
0
Typ.
Max. Units
120
160
120
MHz
MHz
MHz
ns
ns
55
50
50
%
ns
ns
ps
ps
850
ps
Mode dependent
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
0
0.84
0.74
45
50
Deviation from mean
150
60
At VDD/2
Note 1: The phase relationship between input and output clocks can change at power up. Use the ICS570 or
ICS527 Zero Delay Buffers for a guaranteed phase relationship.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
120
115
105
58
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
LOW SKEW CLOCK INVERTER AND DIVIDER
5
ICS548A-03
REV C 063006
MCU
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