Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Excluding Reference
Typically
±
0.0006%
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
¥
f
NOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
¥
f
NOTCH
Output Noise
Integral Nonlinearity @ 25∞C
T
MIN
to T
MAX
Positive Full-Scale Error
2, 3
Full-Scale Drift
5
Unipolar Offset Error
2
Unipolar Offset Drift
5
Bipolar Zero Error
2
Bipolar Zero Drift
5
Gain Drift
Bipolar Negative Full-Scale Error
2
@ 25∞C
T
MIN
to T
MAX
Bipolar Negative Full-Scale Drift
5
ANALOG INPUTS/REFERENCE INPUTS
Normal Mode 50 Hz Rejection
6
Normal Mode 60 Hz Rejection
6
DC Input Leakage Current @ 25∞C
6
T
MIN
to T
MAX
Sampling Capacitance
6
AIN1/REF IN
Common-Mode Rejection (CMR)
Common-Mode Rejection (CMR)
Common-Mode 50 Hz Rejection
6
Common-Mode 60 Hz Rejection
6
Common-Mode Voltage Range
7
Analog Inputs
8
Input Voltage Range
9
At DC and AV
DD
= 5 V
At DC and AV
DD
= 10 V
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±0.02 ¥
f
NOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±0.02 ¥
f
NOTCH
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
Removed by System Calibrations but not by Self-Calibration
max
max
mV max
mV/∞C
typ
V min to V max
Input Sampling Rate, f
S
AIN2 Offset Error
AIN2 Offset Drift
Reference Inputs
REF IN(+) – REF IN(–) Voltage
11
Input Sampling Rate, f
S
REFERENCE OUTPUT
Output Voltage
Initial Tolerance @ 25∞C
Drift
Output Noise
Line Regulation (AV
DD
)
Load Regulation
External Current
For Specified Performance. Part Is Functional with
Lower V
REF
Voltages
V nom
% max
ppm/∞C typ
mV
typ
mV/V max
mV/mA max
mA max
Peak-to-Peak Noise. 0.1 Hz to 10 Hz Bandwidth
Maximum Load Current 1 mA
NOTES
1
Temperature range is as follows: A Version = – 40∞C to +85∞C; S Version = –55∞C to +125∞C. See also Note 16.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part, as shown in Table I, after system calibration. These errors will be 20
mV
typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
These numbers are guaranteed by design and/or characterization.
7
This common-mode voltage range is allowed, provided the input voltage on AIN(+) and AIN(–) does not exceed AV
DD
+ 30 mV and V
SS
– 30 mV.
8
The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resis-
tance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2 input is
with respect to AGND. The absolute voltage on the analog inputs should not go more positive than AV
DD
+ 30 mV, or more negative than V
SS
– 30 mV.
10
V
REF
= REF IN(+) – REF IN(–).
11
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
–2–
REV. G
AD7711
Parameter
V
BIAS
INPUT
Input Voltage Range
12
A, S Versions
1
AV
DD
– 0.85
¥
V
REF
or AV
DD
– 3.5
or AV
DD
– 2.1
V
SS
+ 0.85
¥
V
REF
or V
SS
+ 3
or V
SS
+ 2.1
65 to 85
±
10
0.8
2.0
0.8
3.5
0.4
4.0
±
10
9
4.5
±
10
0.1
200
±
20
20
±
1
3
200
200
AV
DD
– 2
(1.05
¥
V
REF
)/GAIN
–(1.05
¥
V
REF
)/GAIN
–(1.05
¥
V
REF
)/GAIN
0.8
¥
V
REF
/GAIN
(2.1
¥
V
REF
)/GAIN
Unit
Conditions/Comments
See V
BIAS
Input Section
Whichever Is Smaller; +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Smaller; +5 V/0 V Nominal AV
DD
/V
SS
See V
BIAS
Input Section
Whichever Is Greater; +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Greater; +5 V/0 V Nominal AV
DD
/V
SS
Increasing with Gain
V max
V max
V min
V min
dB typ
mA
max
V max
V min
V max
V min
V max
V min
mA
max
pF typ
mA
nom
% typ
%/∞C typ
mA
nom
% max
ppm/∞C typ
% max
ppm/∞C typ
nA/V max
nA/V max
V max
V max
V max
V max
V min
V max
V
BIAS
Rejection
LOGIC INPUTS
Input Current
All Inputs except MCLK IN
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
TRANSDUCER BURNOUT
Current
Initial Tolerance @ 25∞C
Drift
RTD EXCITATION CURRENTS (RTD1, RTD2)
Output Current
Initial Tolerance @ 25∞C
Drift
Initial Matching @ 25∞C
Drift Matching
Line Regulation (AV
DD
)
Load Regulation
Output Compliance
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
Negative Full-Scale Calibration Limit
14
Offset Calibration Limit
15
Input Span
15
I
SINK
= 1.6 mA
I
SOURCE
= 100
mA
Matching between RTD1 and RTD2 Currents
Matching between RTD1 and RTD2 Current Drift
AV
DD
= 5 V
GAIN Is the Selected PGA Gain (between 1 and 128)
GAIN Is the Selected PGA Gain (between 1 and 128)
GAIN Is the Selected PGA Gain (between 1 and 128)
GAIN Is the Selected PGA Gain (between 1 and 128)
GAIN Is the Selected PGA Gain (between 1 and 128)
NOTES
12
The AD7711 is tested with the following V
BIAS
voltages. With AV
DD
= 5 V and V
SS
= 0 V, V
BIAS
= 2.5 V; with AV
DD
= 10 V and V
SS
= 0 V, V
BIAS
= 5 V, and
with AV
DD
= 5 V and V
SS
= –5 V, V
BIAS
= 0 V.
13
Guaranteed by design, not production tested.
14
After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.
15
These calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
REV. G
–3–
AD7711–SPECIFICATIONS
Parameter
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage
16
DV
DD
Voltage
17
AV
DD
– V
SS
Voltage
Power Supply Currents
AV
DD
Current
DV
DD
Current
V
SS
Current
Power Supply Rejection
18
Positive Supply (AV
DD
and DV
DD
)
Negative Supply (V
SS
)
Power Dissipation
Normal Mode
Standby (Power-Down) Dissipation
A, S Versions
1
Unit
Conditions/Comments
5 to 10
5
10.5
4
4.5
1.5
See Note 19
90
45
52.5
15
V nom
V nom
V max
mA max
mA max
mA max
dB typ
dB typ
mW max
mW max
mW max
±
5% for Specified Performance
±
5% for Specified Performance
For Specified Performance
V
SS
= –5 V
Rejection w.r.t. AGND; Assumes V
BIAS
Is Fixed
AV
DD
= DV
DD
= +5 V, V
SS
= 0 V; Typically 25 mW
AV
DD
= DV
DD
= +5 V, V
SS
= –5 V; Typically 30 mW
AV
DD
= DV
DD
= +5 V, V
SS
= 0 V or –5 V; Typically 7 mW
NOTES
16
The AD7711 is specified with a 10 MHz clock for AV
DD
voltages of 5 V
±
5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V. Operating with AV
DD
voltages in the range 5.25 V to 10.5 V is only guaranteed over the 0∞C to 70∞C temperature range.
17
The
±
5% tolerance on the DV
DD
input is allowed provided DV
DD
does not exceed AV
DD
by more than 0.3 V.
18
Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz will exceed
120 dB with filter notches of 10 Hz, 30 Hz, or 60 Hz.
19
PSRR depends on gain: Gain of 1 = 70 dB typ; Gain of 2: 75 dB typ; Gain of 4 = 80 dB typ; Gains of 8 to 128 = 85 dB typ. These numbers can be improved (to
95 dB typ) by deriving the V
BIAS
voltage (via Zener diode or reference) from the AV
DD
supply.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25∞C, unless otherwise noted.)
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300∞C
Power Dissipation (Any Package) to 75∞C . . . . . . . . . . 450 mW
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
AD7711AN
AD7711AR
AD7711AR-REEL
AD7711AR-REEL7
AD7711AQ
AD7711SQ
EVAL-AD7711EB
Temperature Range
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–55∞C to +125∞C
Evaluation Board
Package Option*
N-24
R-24
R-24
R-24
Q-24
Q-24
*N
= Plastic DIP, Q = CERDIP, R = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7711 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. G
AD7711
TIMING CHARACTERISTICS
Parameter
f
CLK IN4, 5
t
CLK IN LO
t
CLK IN HI
t
r6
t
f 6
t
1
Self-Clocking Mode
t
2
t
3
t
4
t
5
t
6
t
7 7
t
8 7
t
9
t
10
t
14
t
15
t
16
t
17
t
18
t
19
400
10
0.4
×
t
CLK IN
0.4
×
t
CLK IN
50
50
1000
0
0
2
×
t
CLK IN
0
4
×
t
CLK IN
+ 20
4
×
t
CLK IN
+ 20
t
CLK IN
/2
t
CLK IN
/2 + 30
t
CLK IN
/2
3
×
t
CLK IN
/2
50
0
4
×
t
CLK IN
+ 20
4
×
t
CLK IN
0
10
1, 2
(DV
DD
= +5 V
5%; AV
DD
= +5 V or +10 V
3
5%; V
SS
= 0 V or –5 V 10%; AGND = DGND =
0 V; f
CLK IN
= 10 MHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless otherwise noted.)
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
Conditions/Comments
Master Clock Frequency: Crystal Oscillator or Externally
Supplied for Specified Performance
Master Clock Input Low Time; t
CLK IN
= 1/f
CLK IN
Master Clock Input High Time
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
SYNC
Pulse Width
DRDY
to
RFS
Setup Time
DRDY
to
RFS
Hold Time
A0 to
RFS
Setup Time
A0 to
RFS
Hold Time
RFS
Low to SCLK Falling Edge
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
A0 to
TFS
Setup Time
A0 to
TFS
Hold Time
TFS
to SCLK Falling Edge Delay Time
TFS
to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
Limit at T
MIN
, T
MAX
(A, S Versions)
2
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
The AD7711 is specified with a 10 MHz clock for AV
DD
voltages of 5 V
±
5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V.
4
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711 is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
5
The AD7711 is production tested with f
CLK IN
at 10 MHz (8 MHz for AV
DD
> 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6
Specified using 10% and 90% points on waveform of interest.
7
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
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