MT9300B
Multi-Channel Voice Echo Canceller
Data Sheet
Not recommended for new designs. Use the
ZL38065, 32 channel VEC with enhanced
algorithm.
March 2005
Ordering Information
MT9300BL
MT9300BV
160 Pin MQFP
208 Ball LBGA
Features
•
Independent multiple channels of echo
cancellation; from 32 channels of 64 ms to 16
channels of 128 ms with the ability to mix
channels at 128 ms or 64 ms in any combination
Independent Power Down mode for each group of
2 channels for power management
ITU-T G.165 and G.168 compliant
Field proven, high quality performance
Compatible to ST-BUS and GCI interface at
2 Mb/s serial PCM
PCM coding,
µ/A-Law
ITU-T G.711 or sign
magnitude
Per channel Fax/Modem G.164 2100 Hz or G.165
2100 Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Fast reconvergence on echo path changes
Non-Linear Processor with high quality subjective
performance
V
DD
V
SS
-40°C to +85°C
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•
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•
•
•
•
Protection against narrow band signal divergence
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
3.3 Volts operation with 5-Volt tolerant inputs
No external memory required
Non-multiplexed microprocessor interface
IEEE-1149.1 (JTAG) Test Access Port
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•
•
•
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•
•
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Applications
•
•
•
•
•
•
Voice over IP network gateways
Voice over ATM, Frame Relay
T1/E1/J1 multichannel echo cancellation
Wireless base stations
Echo Canceller pools
DCME, satellite and multiplexer systems
ODE
Echo Canceller Pool
Rin
Sin
MCLK
Fsel
PLL
Serial
to
Parallel
Group 0
ECA/ECB
Group 1
ECA/ECB
Group 2
ECA/ECB
Group 3
ECA/ECB
Parallel
to
Serial
Rout
Sout
Group 4
ECA/ECB
Group 5
ECA/ECB
Group 6
ECA/ECB
Group 7
ECA/ECB
Group 8
ECA/ECB
Group 9
ECA/ECB
Group 10
ECA/ECB
Group 11
ECA/ECB
Group 12
ECA/ECB
C4i
F0i
Timing
Unit
Group 13
ECA/ECB
Group 14
ECA/ECB
Group 15
ECA/ECB
Note:
Refer to Figure 4
for Echo Canceller
block diagram
Test Port
IC0
RESET
Microprocessor Interface
DS CS R/W A10-A0 DTA
D7-D0
IRQ
TMS TDI TDO TCK TRST
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT9300B
Pin Description
Pin #
208-Ball LBGA
A1,A3,A7,A11,A13,A15, A16, B2,
B6,B8,B12, B14, B15,
B16,C3,C5,C7, C9,C11,C12,
C13,C14, C16, D4,D8,D10,
D12,D13,E3, E4,E14,F13,G3,
G4,G7,G8,G9,G10,H7,H8,H9,
H10,H13, H14,J7,J8,J9, J10,
K7,K8, K9,K10,K13, K14,L3,
L4,M13, M14,,M15,N3,N4,N5,
N7,N9,N11,N13,P2,P3,P5,P7,P9.P
11,P13, P14,R2,R14, R15,R16,T1,
T3,T7,T10, T14,T16
Data Sheet
160 Pin
MQFP
1, 2, 17, 27,
37, 38, 48,
58, 76, 77,
81, 87, 98,
108, 118,
119, 138,
139, 148,
149
Name
V
SS
Ground.
Description
A5,A9,B4,B10,C4,C8,C10,D3,D5, 8, 22, 32,
D7,D9,D11,D14,E13,
43, 53, 63,
F3,F4,F14,H3,H4,J13,J14,L13,L14 79, 93, 103,
,M3,M4,N6,N8, N10,N14,
113, 124,
N15,P4,P6,P8, P10,P15,
141, 142,
R4,R6,R8,R10, R12,T5,T12
159
E15,F15,A12,A10,A6,A2,
B1,B3,C1,C2,D2,E2,J2,K2,R1
57, 59, 114,
115,
116,117,
120,
121,122,
133, 134,
135, 144,
145, 157,
3 to 7, 14 to
16,
28 to 31, 33
to 36,
39 to 42, 60
to 62,
64 to 75, 78,
80,
82 to 86, 88
to 92, 94 to
97, 99
to102, 104,
123,
125 to 132,
136, 137,
150,151,160
9
V
DD1
Positive Power Supply.
Nominally 3.3 volt.
IC0
Internal Connection.
These pins must be connected to
V
SS
for normal operation.
A14,C15,D1,D15,E1,F1, G1,
G15,H1,H15,J1,J15,K1,
K15,L1,L15,F2,L2
NC
No connection.
These pins must be left open for normal
operation.
R9
IRQ
Interrupt Request (Open Drain Output).
This output
goes low when an interrupt occurs in any channel. IRQ
returns high when all the interrupts have been read from
the Interrupt FIFO Register. A pull-up resistor (1 K typical)
is required at this output.
5
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