P2040A
Product Preview
LCD Panel EMI Reduction IC
Product Description
The P2040A is a versatile spread spectrum frequency modulator
designed specifically for digital flat panel applications. The P2040A
reduces electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of down stream clock and data
dependent signals. The P2040A allows significant system cost savings
by reducing the number of circuit board layers, ferrite beads,
shielding, and other passive components that are traditionally required
to pass EMI regulations.
The P2040A uses the most efficient and optimized modulation
profile approved by the FCC and is implemented in a proprietary all
digital method.
The P2040A modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more importantly,
decreases the peak amplitudes of its harmonics. This results in
significantly lower system EMI compared to the typical narrow band
signal produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
Features
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SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
PIN CONFIGURATION
CLKIN
MRA
SR1
VSS
(Top View)
1
VDD
P2040A
SR0
ModOUT
SSON#
•
FCC Approved Method of EMI Attenuation
•
Provides up to 20 dB of EMI Suppression
•
Generates a Low EMI Spread Spectrum Clock of the Input
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ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Frequency
Input Frequency Range: 30 MHz to 100 MHz
3.3 V Operating Voltage
Optimized for VGA, SVGA, and Higher Resolution XGA LCD
Panels
Internal Loop Filter Minimizes External Components and Board
Space
Six Selectable High Spread Ranges up to
±2%
Two Selectable Modulation Rates
SSON# Control Pin for Spread Spectrum Enable and Disable Options
Low Cycle−to−Cycle Jitter
Wide Operating Range
Low Power CMOS Design
Supports Most Mobile Graphic Accelerator Specifications
Products Available for Automotive Temperature Range. (Refer to
Spread Range Selection
Tables)
Available in 8−pin SOIC and TSSOP Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. P3
1
Publication Order Number:
P2040A/D
P2040A
SR0 SR1 MRA SSON#
VDD
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
1
2
3
4
5
6
7
8
Pin Name
CLKIN
MRA
SR1
VSS
SSON#
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull−up resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function
enabled when LOW, disabled when HIGH. This pin has an internal pull−low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor.
Power supply for the entire chip (3.3 V).
Table 2. MODULATION SELECTION (Commercial)
MRA
0
0
0
0
1
1
1
1
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range
±1.125
±1.75
±0.75
±1.25
±1.25
±2.00
Reserved
Reserved
Modulation Rate (KHz)
(FIN /40) * 34.72 KHz
(FIN /40) * 34.72 KHz
(FIN /40) * 34.72 KHz
(FIN /40) * 34.72 KHz
(FIN /40) * 20.83 KHz
(FIN /40) * 20.83 KHz
Reserved
Reserved
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P2040A
Table 3. SPREAD RANGE SELECTION AT 50 MHz (Automotive)
MRA
0
0
0
0
1
1
1
1
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range
±1.25
±2.00
±1.00
±1.50
±1.25
±2.00
±1.25
±2.00
Modulation Rate
(F
IN
/40) * 34.72 KHz
(F
IN
/40) * 34.72 KHz
(F
IN
/40) * 34.72 KHz
(F
IN
/40) * 34.72 KHz
(F
IN
/40) * 20.83 KHz
(F
IN
/40) * 20.83 KHz
(F
IN
/40) * 20.83 KHz
(F
IN
/40) * 20.83 KHz
Table 4. SPREAD RANGE SELECTION AT 70 MHz (Automotive)
MRA
0
0
0
0
1
1
1
1
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range
±1.00
±1.50
±0.70
±1.00
±1.15
±2.00
±1.15
±1.75
Modulation Rate
(F
IN
/40) * 34.72 KHz
(F
IN
/40) * 34.72 KHz
(F
IN
/40) * 34.72 KHz
(F
IN
/40) * 34.72 KHz
(F
IN
/40) * 20.83 KHz
(F
IN
/40) * 20.83 KHz
(F
IN
/40) * 20.83 KHz
(F
IN
/40) * 20.83 KHz
Spread Spectrum Selection
The
Modulation Selection
Table defines the possible
spread spectrum options. The optimal setting should
minimize system EMI to the fullest without affecting system
performance. The spreading is described as a percentage
deviation of the center frequency. (Note: The center
frequency is the frequency of the external reference input on
CLKIN, pin1).
For example, P2040A is designed for high−resolution, flat
panel applications and is able to support an XGA (1024 x
768) flat panel operating at 65 MHz (F
IN
) clock speed. A
spreading selection of MRA=0, SR1=1 and SR0=0 provides
a percentage deviation of
±0.75%
from F
IN
. This results in
the frequency on ModOUT being swept from 64.51 MHz to
65.49 MHz at a modulation rate of 56.24 KHz. Refer to
Modulation Selection
Table. The example in the following
illustration is a common EMI reduction method for a
notebook LCD panel and has already been implemented by
most of the leading OEM and mobile graphic accelerator
manufacturers.
+3.3 V
65 MHz from graphics accelerator.
1 CLKIN
2 MRA
3 SR1
4 VSS
VDD 8
SR0 7
ModOUT 6
0.1
mF
Modulated 65 MHz signal with
±0.75
deviation and modulation
rate of 56.24 KHz. This signal is
connected back to the spread
spectrum input pin (SSIN) of
the graphics accelerator.
SSON# 5
P2040A
Digital control for the SS enable
or disable.
Figure 2. Application Schematic for Mobile LCD Graphics Controllers
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P2040A
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Parameter
Voltage on any pin with respect to Ground
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +4.6
−65
to +125
−40
to +125
260
150
2
Unit
V
°C
°C
°C
°C
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 6. DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
VDD
t
ON
Z
OUT
Input low voltage
Input high voltage
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated.)
Parameter
Min
VSS−0.3
2.0
−35
−
−
2.5
−
7
2.7
−
−
Typ
−
−
−
−
−
−
0.6
10
3.3
0.18
50
Max
0.8
VDD+0.3
−
35
0.4
−
−
13
3.7
−
−
Unit
V
V
mA
mA
V
V
mA
mA
V
mS
W
Input low current
(pull−up resistor on inputs SR0, SR1 and MRA)
Input high current (pull−down resistor on input SSON#)
Output low voltage (VDD = 3.3 V, I
OL
= 20 mA)
Output high voltage (VDD = 3.3 V, I
OH
= 20 mA)
Static supply current standby mode
Dynamic supply current (3.3 V and 10 pF loading)
Operating voltage
Power−up time (first locked cycle after power up)
Clock output impedance
Table 7. AC ELECTRICAL CHARACTERISTICS
Symbol
f
IN
f
OUT
t
LH
(Note 1)
t
HL
(Note 1)
t
JC
t
D
Input frequency
Output frequency
Output rise time (measured at 0.8 V to 2.0 V)
Output fall time (measured at 2.0 V to 0.8 V)
Jitter (cycle−to−cycle)
Output duty cycle
Parameter
Min
30
30
0.7
0.6
−
45
Typ
−
−
0.9
0.8
−
50
Max
100
100
1.1
1.0
360
55
Unit
MHz
MHz
nS
nS
pS
%
1. t
LH
and t
HL
are measured into a capacitive load of 15 pF
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P2040A
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
A
A1
A2
b
E1
E
c
D
E
E1
e
L
L1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
NOM
MAX
1.20
0.15
0.90
1.05
0.30
0.20
3.00
6.40
4.40
0.65 BSC
1.00 REF
3.10
6.50
4.50
0.50
0.60
0.75
θ
e
0º
8º
TOP VIEW
D
A2
A
q1
c
A1
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
L1
END VIEW
L
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