ADVANCE
‡
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
FLASH MEMORY
FEATURES
• Single device supports asynchronous, page, and
burst operations
• Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank
a
during program bank
b
and vice
versa
Read bank
a
during erase bank
b
and vice versa
• Basic configuration:
One hundred and thirty-five erasable blocks
Bank
a
(16Mb for data storage)
Bank
b
(48Mb for program storage)
• V
CC
, V
CC
Q, V
PP
voltages
1.70V (MIN), 1.90V (MAX) V
CC
, V
CC
Q
(MT28F642D18 only)
1.80V (MIN), 2.20V (MAX) V
CC
, and
2.25V (MAX) V
CC
Q (MT28F642D20 only)
1.80V (TYP) V
PP
(in-system PROGRAM/ERASE)
12V ±5% (HV) V
PP
tolerant (factory programming
compatibility)
• Random access time: 70ns @ 1.80V V
CC
1
• Burst Mode read access
MAX clock rate: 54 MHz (
t
CLK = 18.5ns)
Burst latency: 70ns @ 1.80V V
CC
and 54 MHz
t
ACLK: 15ns @ 1.80V V
CC
and 54 MHz
• Page Mode read access
1
Four-/eight-word page
Interpage read access: 70ns @ 1.80V
Intrapage read access: 30ns @ 1.80V
• Low power consumption (V
CC
= 2.20V)
Asynchronous Read < 15mA
Interpage Read < 15mA
Intrapage Read < 5mA
Continuous Burst Read < 10mA
WRITE < 55mA (MAX)
ERASE < 45mA (MAX)
Standby < 50µA (MAX)
Automatic power save (APS) feature
Deep power-down < 25µA (MAX)
• Enhanced write and erase suspend options
• Accelerated programming algorithm (APA) in-
system and in-factory
• Dual 64-bit chip protection registers for security
purposes
NOTE:
1. Data based on MT28F642D20 device.
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
MT28F642D18
MT28F642D20
Low Voltage, Extended Temperature
0.18µm Process Technology
PIN ASSIGNMENT
59-Ball FBGA
1
A
B
C
D
E
F
G
A11
2
A8
3
V
SS
4
V
CC
5
V
PP
6
A18
7
A6
8
A4
A12
A9
A20
CLK
RST#
A17
A5
A3
A13
A10
A21
ADV#
WE#
A19
A7
A2
A15
A14
WAIT#
A16
DQ12
WP#
A1
V
CC
Q
DQ15
DQ6
DQ4
DQ2
DQ1
CE#
A0
V
SS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
OE#
DQ7
V
SS
Q
DQ5
V
CC
DQ3
V
CC
Q
DQ8
V
SS
Q
Top View
(Ball Down)
NOTE:
See page 7 for Ball Description Table.
See page 50 for mechanical drawing.
• Cross-compatible command support
Extended command set
Common flash interface
• PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
OPTIONS
• Timing
80ns access
70ns access
• Frequency
40 MHz
54 MHz
• Boot Block Configuration
Top
Bottom
• Package
59-ball FBGA (8 x 7 ball grid)
• Operating Temperature Range
Extended (-40ºC to +85ºC)
Part Number Example:
MARKING
-80
-70
4
5
T
B
FN
ET
MT28F642D20FN-804 TET
1
©2002, Micron Technology, Inc.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
GENERAL DESCRIPTION
The MT28F642D20 and MT28F642D18 are high-
performance, high-density, nonvolatile memory solu-
tions that can significantly improve system
performance. This new architecture features a two-
memory-bank configuration that supports dual-bank
operation with no latency.
A high-performance bus interface allows a fast burst
or page mode data transfer; a conventional asynchro-
nous bus interface is provided as well.
The devices allow soft protection for blocks, as read-
only, by configuring soft protection registers with dedi-
cated command sequences. For security purposes, two
64-bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to moni-
tor the WSM status and to determine the progress of
the program/erase task.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
ware packages.
These devices are manufactured using 0.18µm pro-
cess technology.
Please refer to the Micron Web site (www.micron.com/
flash)
for the latest data sheet.
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash devices contain two separate banks of
memory (bank
a
and bank
b)
for simultaneous READ
and WRITE operations, which are available in the fol-
lowing bank segmentation configurations:
• Bank
a
comprises one-fourth of the memory and
contains 8 x 4K-word parameter blocks and
31 x 32K-word blocks.
• Bank
b
represents three-fourths of the memory, is
equally sectored, and contains 96 x 32K-word
blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to the Micron part
numbers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28F642D20FN-705 TET
MT28F642D20FN-705 BET
MT28F642D20FN-804 TET
MT28F642D20FN-804 BET
MT28F642D18FN-705 TET
MT28F642D18FN-705 BET
MT28F642D18FN-804 TET
MT28F642D18FN-804 BET
PRODUCT
MARKING
FW906
FW905
FW907
FW908
FW909
FW910
FW911
FW912
SAMPLE
MARKING
FX906
FX905
FX907
FX908
FX909
FX910
FX911
FX912
MECHANICAL
SAMPLE MARKING
FY906
FY905
FY907
FY908
FY909
FY910
FY911
FY912
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
PART NUMBERING INFORMATION
Micron’s low-power devices are available with sev-
eral different combinations of features (see Figure 1).
Valid combinations of features and their correspond-
ing part numbers are listed in Table 2.
Figure 1
Part Number Chart
MT 28F 642 D20 FN-80 4 B ET
Micron Technology
Flash Family
28F = Dual-Supply Flash
Operating Temperature Range
ET = Extended (-40ºC to +85ºC)
Boot Block Starting Address
B = Bottom boot
T = Top boot
Density/Organization/Banks
642 = 64Mb (4,096K x 16)
bank
a
= 1/4; bank
b
= 3/4
Burst Mode Frequency
4 = 40 MHz
5 = 54 MHz
Read Mode Operation
D = Asynchronous/Page/Burst Read
Access Time
-70 = 70ns
-80 = 80ns
Operating Voltage Range
18 = 1.70V–1.90V
20 = 1.80V–2.20V V
CC
20 = 1.80V–2.25V V
CC
Q
Package Code
FN = 59-ball FBGA (8 x 7 grid)
Table 2
Valid Part Number Combinations
1
ACCESS
TIME (ns)
70
70
80
80
70
70
80
80
BOOT BLOCK
STARTING
ADDRESS
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
BURST
FREQUENCY
(MHz)
54
54
40
40
54
54
40
40
OPERATING
TEMPERATURE
RANGE
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
PART NUMBER
MT28F642D20FN-705 TET
MT28F642D20FN-705 BET
MT28F642D20FN-804 TET
MT28F642D20FN-804 BET
MT28F642D18FN-705 TET
MT28F642D18FN-705 BET
MT28F642D18FN-804 TET
MT28F642D18FN-804 BET
NOTE:
1. For part number combinations not listed in this table, please contact your Micron
representative.
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
PR Lock
PR Lock
Query
Query/OTP
OTP
DQ0–DQ15
X DEC
Data Input
Buffer
Data
Register
RST#
CE#
WE#
OE#
Y/Z DEC
Bank 1 Blocks
Y/Z Gating/Sensing
Manufacturer’s ID
Device ID
Block Lock
RCR
ID Reg.
CSM
Status
Reg.
WSM
Program/
Erase
Pump Voltage
Generators
Output
Multiplexer
DQ0–DQ15
I/O Logic
Output
Buffer
A0–A21
Address
Input
Buffer
Address
CNT WSM
WAIT#
Address
Multiplexer
Y/Z DEC
X DEC
Y/Z Gating/Sensing
Bank 2 Blocks
ADV#
Address Latch
CLK
BSM
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 2
Bottom Boot Block Device
Block
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
Bank
b
= 48Mb
Block Size
Address Range
(K-bytes/
(x16)
K-words)
64/32
3F8000h–3FFFFFh
64/32
3F0000h–3F7FFFh
64/32
3E8000h–3EFFFFh
64/32
3E0000h–3E7FFFh
64/32
3D8000h–3DFFFFh
64/32
3D0000h–3D7FFFh
64/32
3C8000h–3CFFFFh
64/32
3C0000h–3C7FFFh
64/32
3B8000h–3BFFFFh
64/32
3B0000h–3B7FFFh
64/32
3A8000h–3AFFFFh
64/32
3A0000h–3A7FFFh
64/32
398000h–39FFFFh
64/32
390000h–397FFFh
64/32
388000h–38FFFFh
64/32
380000h–387FFFh
64/32
378000h–37FFFFh
64/32
370000h–377FFFh
64/32
368000h–36FFFFh
64/32
360000h–367FFFh
64/32
358000h–35FFFFh
64/32
350000h–357FFFh
64/32
348000h–34FFFFh
64/32
340000h–347FFFh
64/32
338000h–33FFFFh
64/32
330000h–337FFFh
64/32
328000h–32FFFFh
64/32
320000h–327FFFh
64/32
318000h–31FFFFh
64/32
310000h–317FFFh
64/32
308000h–30FFFFh
64/32
300000h–307FFFh
64/32
2F8000h–2FFFFFh
64/32
2F0000h–2F7FFFh
64/32
2E8000h–2EFFFFh
64/32
2E0000h–2E7FFFh
64/32
2D8000h–2DFFFFh
64/32
2D0000h–2D7FFFh
64/32
2C8000h–2CFFFFh
64/32
2C0000h–2C7FFFh
64/32
2B8000h–2BFFFFh
64/32
2B0000h–2B7FFFh
64/32
2A8000h–2AFFFFh
64/32
2A0000h–2A7FFFh
64/32
298000h–29FFFFh
64/32
290000h–297FFFh
64/32
288000h–28FFFFh
64/32
280000h–287FFFh
Block
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
Bank
b
= 48Mb
Block Size
Address Range
(K-bytes/
(x16)
K-words)
64/32
278000h–27FFFFh
64/32
270000h–277FFFh
64/32
268000h–26FFFFh
64/32
260000h–267FFFh
64/32
258000h–25FFFFh
64/32
250000h–257FFFh
64/32
248000h–24FFFFh
64/32
240000h–247FFFh
64/32
238000h–23FFFFh
64/32
230000h–237FFFh
64/32
228000h–22FFFFh
64/32
220000h–227FFFh
64/32
218000h–21FFFFh
64/32
210000h–217FFFh
64/32
208000h–20FFFFh
64/32
200000h–207FFFh
64/32
1F8000h–1FFFFFh
64/32
1F0000h–1F7FFFh
64/32
1E8000h–1EFFFFh
64/32
1E0000h–1E7FFFh
64/32
1D8000h–1DFFFFh
64/32
1D0000h–1D7FFFh
64/32
1C8000h–1CFFFFh
64/32
1C0000h–1C7FFFh
64/32
1B8000h–1BFFFFh
64/32
1B0000h–1B7FFFh
64/32
1A8000h–1AFFFFh
64/32
1A0000h–1A7FFFh
64/32
198000h–19FFFFh
64/32
190000h–197FFFh
64/32
188000h–18FFFFh
64/32
180000h–187FFFh
64/32
178000h–17FFFFh
64/32
170000h–177FFFh
64/32
168000h–16FFFFh
64/32
160000h–167FFFh
64/32
158000h–15FFFFh
64/32
150000h–157FFFh
64/32
148000h–14FFFFh
64/32
140000h–147FFFh
64/32
138000h–13FFFFh
64/32
130000h–137FFFh
64/32
128000h–12FFFFh
64/32
120000h–127FFFh
64/32
118000h–11FFFFh
64/32
110000h–117FFFh
64/32
108000h–10FFFFh
64/32
100000h–107FFFh
Block
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bank
a
= 16Mb
Block Size
Address Range
(K-bytes/
(x16)
K-words)
64/32
0F8000h–0FFFFFh
64/32
0F0000h–0F7FFFh
64/32
0E8000h–0EFFFFh
64/32
0E0000h–0E7FFFh
64/32
0D8000h–0DFFFFh
64/32
0D0000h–0D7FFFh
64/32
0C8000h–0CFFFFh
64/32
0C0000h–0C7FFFh
64/32
0B8000h–0BFFFFh
64/32
0B0000h–0B7FFFh
64/32
0A8000h–0AFFFFh
64/32
0A0000h–0A7FFFh
64/32
098000h–09FFFFh
64/32
090000h–097FFFh
64/32
088000h–08FFFFh
64/32
080000h–087FFFh
64/32
078000h–07FFFFh
64/32
070000h–077FFFh
64/32
068000h–06FFFFh
64/32
060000h–067FFFh
64/32
058000h–05FFFFh
64/32
050000h–057FFFh
64/32
048000h–04FFFFh
64/32
040000h–047FFFh
64/32
038000h–03FFFFh
64/32
030000h–037FFFh
64/32
028000h–02FFFFh
64/32
020000h–027FFFh
64/32
018000h–01FFFFh
64/32
010000h–017FFFh
64/32
008000h–00FFFFh
8/4
007000h–007FFFh
8/4
006000h–006FFFh
8/4
005000h–005FFFh
8/4
004000h–004FFFh
8/4
003000h–003FFFh
8/4
002000h–002FFFh
8/4
001000h–001FFFh
8/4
000000h–00FFFh
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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