T6B70BF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6B70BF
Interface IC for Water Heater
The T6B70BF incorporates two-channel 4-bit DA converter, a
pseudo sine wave generator and an external analog signal
detection/non-detection circuit. It is designed to be used mainly
for communication between water heater and control unit.
Features
·
·
·
·
On-chip two-channel 4-bit DA converter (opposite polarities)
On-chip pseudo sine wave generator (external clock/16)
On-chip external analog signal detection/non-detection circuit
On-chip two-channel analog switch
Weight: 0.16 g (typ.)
Block Diagram
OSCIN 1
OSCOUT 2
FOUT 3
SCTL
Divide-by-
16 unit
Pseudo
sine wave
generator
0°C
180°C
4-bit
DA converter
4-bit
DA converter
13 SOUT+
12 SOUT−
16 V
DD
Waveform
initialization block
4
Modulation
control circuit
Zero-cross
waveform
shaping circuit
Amplifier input
circuit
SW1IN 14
SW1OUT 15
7 AMPIN
6 AMPOUT
Cycle measurement counter
SW2IN 11
SW2OUT 10
RESET
Analog signal
detection/non-detection
Reset
circuit
Output buffer
8 V
SS
9
DOUT
5
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T6B70BF
Pin Assignment
OSCIN
OSCOUT
FOUT
SCTL
RESET
1
2
3
4
T6B70BF
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
SW1OUT
SW1IN
SOUT+
SOUT−
SW2IN
SW2OUT
DOUT
AMPOUT
AMPIN
V
SS
Pin Function
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
OSCIN
OSCOUT
FOUT
SCTL
RESET
Input/Output
Input
Output
Output
Input
Input
Output
Input
―
Output
Output
Input
Output
Output
Input
Output
―
Function
Pins connected to oscillation
Pins connected to oscillation
Output pin for oscillation waveform shaping
circuit
Modulation control signal input pin
Reset signal input pin
Amplifier signal output pin
Amplifier signal input pin
Device GND pin (0 V)
Output pin for amplifier input signal detector
Output pin on analog SW2 side
Input pin on analog SW2 side
Pseudo sine wave (opposite polarity of
SOUT+ output) output pin
Pseudo sine wave output pin
Input pin on analog SW1 side
Output pin on analog SW1 side
Device power supply pin (+5 V)
AMPOUT
AMPIN
V
SS
DOUT
SW2OUT
SW2IN
SOUT−
SOUT+
SW1IN
SW1OUT
V
DD
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T6B70BF
Function Description
(1)
Pseudo sine wave generator and 4-bit DA converters (sending block)
Pseudo sine wave signal with Fosc/16 frequency is driven out from pseudo sine wave output pin
(SOUT+ and SOUT−).
The outputs of pins SOUT+ and SOUT− have the opposite polarities.
The block of pseudo sine wave generator and 4-bit DA converter (the side of SOUT+ pin) are shown
below.
SOUT+ pin
MSB
Pseudo sine wave generator
R
R
R
SOUT+
R
R
R
R
LSB
R
R
SOUT−
FOSC
RST
V
SS
The data of pseudo sine wave generator is driven out in the following sequence.
0
→
1
→
3
→
6
→
9
→
C
→
E
→
F
→
F
→
E
→
C
→
9
→
6
→
3
→
1
→
0 (in hexadecimal)
FF
E
C
E
C
2R
9
R
R
9
6
3
0 1
FSIN
250 kHz
@FOSC = 4 MHz
6
3
1 0
Thus, the pseudo sine waveform of positive-going and negative-going outputs is like a staircase at
no load.
An analog switch is incorporated so that the driver output buffer is connected to the transmission
line only when transmission is performed.
However, an emitter follower circuit is externally connected to the driver output buffer.
The phase difference between positive-going and negative-going outputs is within 180° ± 5°. (pseudo
sine wave output phase fluctuation)
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T6B70BF
(2)
Amplifier input circuit and signal detection/non-detection circuit (receiving block)
The modulation signal input block incorporates two level comparators having a high and a low
threshold values to detect the external sine wave signal with amplitude higher than the specified
threshold. Thus, it avoids signals with amplitude lower than the specified threshold (e.g., noise
signals) being detected erroneously.
The detection frequency range (frequency window) is determined by the divider ratio 1/18 to 1/14 of
Fosc.
In detection/non-detection determined condition, when the signals within the specified frequency
range are detected (or not detected) sequentially, signals are controlled using the majority rule. The
time which detection/non-detection is determined takes 9 to 15 waves to pass when one wave is
referenced to Fosc/16 frequency.
V
DD
R1
APU
V
DD
Reference
voltage
VH
RESET
High comparator
VA
R
Q
Cycle
measurement
counter
APD
R3
7
AMPIN pin
Reference
voltage
VL
VBIAS
Low comparator
VB
S
Q
RESET
Analog
signal
detection
9
/non-
detection
DOUT
pin
circuit
R4
R2
V
SS
V
SS
V
DD
6
AMPOUT pin
AMPIN input sine waveform
VH
Input
sensitivity
V
PP
VL
Detect reception
Not detect reception
Not detect reception
Not detect reception
AMPOUT output timing (when
RESET
is Low)
VH
VBIAS
AMPOUT Truth Table
VA
VBIAS > VH
VH > VBIAS > VL
L
H
H
VB
H
H
L
AMPOUT
L
Hold
H
VL
Held at High
Held at Low
VBIAS < VL
AMPOUT
VBIAS < VL
VBIAS > VH
VH > VBIAS > VL VH > VBIAS > VL
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T6B70BF
(3)
Function description and timing chart of the sending block
When modulation control input (
SCTL
) is in High-level, pseudo sine wave output is held at 0° of
the phase angle of pseudo sine wave. When modulation control input changes from High-level to
Low-level, the pseudo sine wave output (SOUT+) starts from
−90°
(SOUT− starts from +90°).
In this case, the time which takes to turn ON is as follows.
td (ON) < 500 ns
When modulation control input changes from Low-level to High-level, the phase angle is forcibly
held at 0°, regardless of the phase of the pseudo sine wave output. (the pseudo sine wave output is
stopped). In this case, the time which takes to turn OFF is as follows.
td (OFF) < 1 µs
SCTL
td (ON)
SOUT+ pseudo sine wave output
(SOUT− output pin has the
opposite polarity)
td (OFF)
(4)
Function description and timing chart of the receiving block
When it is ready to receive amplifier input signal, the time T (DET) which takes to change from
High to Low at
DOUT
pin is within the time which 9 to 15 waves to pass. In this case, one wave is
referenced to 16 Fosc clocks. The time width is determined by the internal clock and amplifier input
signal. The timings of the internal clock and internal detection signal in the majority logic circuit are
synchronous with each other. When input signals with the cycle, which is within the range specified
by the frequency window, are detected (or not detected) sequentially, this rule is valid (the majority
rule).
Amplifier input
T (DET)
T (DET)
DOUT
Note 1: Any communication protocol is used, however, it takes 15 carrier waves to pass when the signal changes its
state.
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