®
X4283, X4285
128K, 16K x 8 Bit
Data Sheet
May 23, 2006
FN8121.1
CPU Supervisor with 128K EEPROM
FEATURES
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
—Four standard reset threshold voltages
—Adjust low V
CC
reset threshold voltage using
special programming sequence
—Reset signal valid to V
CC
= 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 128Kbits of EEPROM
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock
™
protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SDA
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
Block Lock Control
Protect Logic
Status
Register
EEPROM Array
DESCRIPTION
The X4283, X4285 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V
CC
falls below the set minimum V
CC
trip point. RESET/RESET is asserted until V
CC
returns
to proper operating level and stabilizes. Four industry
standard Vtrip thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
Watchdog
Timer Reset
RESET (X4283)
RESET (X4285)
Reset &
Watchdog
Timebase
S0
S1
8Kb 4Kb 4Kb
SCL
V
CC
V
TRIP
+
-
Power-on and
Low Voltage
Reset
Generation
Kb=Kilobyte
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X4283, X4285
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as 64 bytes per page.
The device features an 2-wire interface and software
protocol allowing operation on an 2-wire bus.
PIN CONFIGURATION
8-Pin JEDEC SOIC
S
0
S
1
RST/RST
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
8-Pin TSSOP
WP
V
CC
S
0
S
1
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
RST/RST
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
Name
S
0
S
1
RESET/
Device Select Input
Device Select Input
Function
RESET
Reset Output.
RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
CC
falls below the minimum V
CC
sense level. It will remain ac-
tive until V
CC
rises above the minimum V
CC
sense level for 250ms. RESET/RESET
goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW
longer than the selectable Watchdog time out period. A falling edge on SDA, while
SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up
and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is al-
ways active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
Supply Voltage
4
5
6
7
V
SS
SDA
6
7
8
8
1
2
SCL
WP
V
CC
2
FN8121.1
May 23, 2006
X4283, X4285
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X4283S8-2.7
PART
MARKING
X4283 F
PART NUMBER
RESET
(ACTIVE HIGH)
X4285S8-2.7
X4285S8Z-2.7
(Note)
X4285S8I-2.7
X4285S8IZ-2.7
(Note)
X4285V8-2.7
X4285V8Z-2.7
(Note)
X4285V8I-2.7
X4285V8IZ-2.7
(Note)
X4285S8-2.7A
PART
V
CC
RANGE V
TRIP
RANGE
TEMP
MARKING
(V)
(V)
RANGE (°C)
X4285 F
X4285 ZF
X4285 G
X4285 ZG
4285 F
4285 FZ
4285 G
4285 GZ
X4285 AN
X4285 ZAN
X4285 AP
X4285 ZAP
4285 AN
4285 ANZ
4285 AP
4285 APZ
X4285
X4285 Z
X4285 I
4.5 to 5.5
4.5 to 4.75
2.85 to 3.0
2.7 to 5.5
2.55 to 2.7
0 to 70
0 to 70
-40 to +85
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
0 to 70
0 to 70
-40 to +85
PACKAGE
8 Ld SOIC
(150 mil)
PKG.
DWG #
MDP0027
X4283S8Z-2.7 (Note) X4283 ZF
X4283S8I-2.7
X4283S8IZ-2.7
(Note)
X4283V8-2.7
X4283 G
X4283 ZG
4283 F
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
X4283V8Z-2.7 (Note) 4283 FZ
X4283V8I-2.7
X4283V8IZ-2.7
(Note)
X4283S8-2.7A*
X4283S8Z-2.7A
(Note)
X4283S8I-2.7A*
X4283S8IZ-2.7A*
(Note)
X4283V8-2.7A
X4283V8Z-2.7A
(Note)
X4283V8I-2.7A
X4283V8IZ-2.7A
(Note)
X4283S8
X4283S8Z (Note)
X4283S8I
X4283S8IZ (Note)
X4283V8
X4283V8Z (Note)
X4283V8I
4283 G
4283 GZ
X4283 AN
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4283 ZAN X4285S8Z-2.7A
(Note)
X4283 AP
X4285S8I-2.7A
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4283 ZAP X4285S8IZ-2.7A
(Note)
4283 AN
4283 ANZ
4283 AP
4283 APZ
X4283
X4283 Z
X4283 I
X4283 ZI
4283
4283 Z
4283 I
X4285V8-2.7A
X4285V8Z-2.7A
(Note)
X4285V8I-2.7A
X4285V8IZ-2.7A
(Note)
X4285S8
X4285S8Z (Note)
X4285S8I
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4285S8IZ (Note) X4285 ZI
X4285V8
X4285V8Z (Note)
X4285V8I
4285
4285 Z
4285 I
MDP0027
8 Ld SOIC
(150 mil) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
M8.173
8 Ld TSSOP
(4.4mm) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
3
FN8121.1
May 23, 2006
X4283, X4285
Ordering Information
(Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X4283V8IZ (Note)
X4283S8-4.5A
X4283S8Z-4.5A
(Note)
X4283S8I-4.5A
X4283S8IZ-4.5A
(Note)
X4283V8-4.5A
X4283V8Z-4.5A
(Note)
X4283V8I-4.5A
X4283V8IZ-4.5A
(Note)
PART
MARKING
4283 IZ
X4283 AL
PART NUMBER
RESET
(ACTIVE HIGH)
PART
V
CC
RANGE V
TRIP
RANGE
TEMP
MARKING
(V)
(V)
RANGE (°C)
4.5 to 5.5
4.5 to 4.75
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
PACKAGE
PKG.
DWG #
X4285V8IZ (Note) 4285 IZ
X4285S8-4.5A
X4285 AL
X4285 ZAL
X4285 AM
X4285 ZAM
4285 AL
4285 ALZ
4285 AM
4285 AMZ
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4283 ZAL X4285S8Z-4.5A
(Note)
X4283 AM
X4285S8I-4.5A
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4283 ZAM X4285S8IZ-4.5A
(Note)
4283 AL
4283 ALZ
4283 AM
4283 AMZ
X4285V8-4.5A
X4285V8Z-4.5A
(Note)
X4285V8I-4.5A
X4285V8IZ-4.5A
(Note)
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4
FN8121.1
May 23, 2006
X4283, X4285
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4283, X4285 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-
up.
When V
CC
exceeds the device V
TRIP
threshold value
for
200ms
(nominal)
the
circuit
releases
RESET/RESET allowing the system to begin opera-
tion.
LOW VOLTAGE MONITORING
During operation, the X4283, X4285 monitors the V
CC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET/RESET signal. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time-Out, any
in-progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Non-volatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
CC
THRESHOLD RESET PROCEDURE
The X4283, X4285 is shipped with a standard V
CC
threshold (V
TRIP
) voltage. This value will not change
over normal operating and storage conditions. How-
ever, in applications where the standard V
TRIP
is not
exactly right, or if higher precision is needed in the
V
TRIP
value, the X4283, X4285 threshold may be
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
Figure 1. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
WP
V
P
= 12-15V
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
SDA
A0h
00h
01h
00h
5
FN8121.1
May 23, 2006
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