EEWORLDEEWORLDEEWORLD

Part Number

Search

PT06W-24-61P025

Description
Circular MIL Spec Connector
CategoryThe connector   
File Size2MB,80 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Download Datasheet Parametric View All

PT06W-24-61P025 Online Shopping

Suppliers Part Number Price MOQ In stock  
PT06W-24-61P025 - - View Buy Now

PT06W-24-61P025 Overview

Circular MIL Spec Connector

PT06W-24-61P025 Parametric

Parameter NameAttribute value
Product CategoryCircular MIL Spec Connector
ManufacturerAmphenol
Number of Positions61 Position
Insert Arrangement24-61
Contact GenderPin (Male)
MIL TypeMIL-DTL-26482
ProductPlugs
Shell Size24
Shell StyleIn-Line
Mounting StyleWire
Termination StyleSolder
Mating StyleBayonet
Mounting AngleStraight
Shell MaterialAluminum Alloy
Shell PlatingNon-Conductive Black Zinc
Amphenol Miniature Cylindrical
Connectors
12-070-15
®
Meets MIL-C-26482, Series 1
Specifications
Amphenol
I am new to 51 MCU. I need help with assembly and C language code of electronic clock with function key control.
[i=s]This post was last edited by firstsea on 2015-11-25 16:06[/i] [align=left][font=黑体][size=19px][b]I am new to 51 MCU and need help with assembly and C language code of electronic clock with functi...
firstsea 51mcu
Problems encountered in Xilinx simulation
Started : "Creating Tbw file". ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "0"'. Tcl_ErrnoId: unknown error Tcl_ErrnoMsg: No error _cmd: ::xilinx::Dpm::dpm_ch...
eeleader FPGA/CPLD
[Uncle T's Library] "Analysis and Design of Analog Integrated Circuits (Fourth Edition)"
[p=24, null, left][color=rgb(86, 86, 86)][backcolor=rgb(237, 235, 235)][font=微软雅黑][size=14px][url=https://download.eeworld.com.cn/detail/tyw/301799?src=2114][color=#0066cc]Chinese version: "Analysis a...
tyw Download Centre
Motion Estimation Algorithm Design and FPGA Implementation.pdf
Motion Estimation Algorithm Design and FPGA Implementation.pdf...
zxopenljx FPGA/CPLD
Question: The problem of unstable sampling on the rising edge of the clock
A very simple code written in Verilog, roughly: reg[1:0] q; //q is the data generated by calling the IP core fifo, the default is reg type output assign data_out={{4{q[0]}},{4{q[1]}}}; //data_out is t...
xyw FPGA/CPLD
Why does the network port chip (971) have the function of encoding and decoding?
So the data sent out through the network port chip is not the original data given by the CPU?...
mbwr Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1895  1450  1484  450  648  39  30  10  14  57 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号