E2B0041-27-Y3
¡ Semiconductor
¡ Semiconductor
MSM9000B-xx
DOT MATRIX LCD CONTROLLER
This version: Nov. 1997
MSM9000B-xx
Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM9000B-xx is a dot-matrix LCD control driver which has functions of displaying 12 (5
x 7 dots) characters (2 lines) and 120-dot arbitrators.
The MSM9000B-xx is provided with a 16-dot common driver, 60-dot segment driver, Display
Data RAM (DDRAM), and Character Generator ROM (CGROM).
This device can be controlled with commands entered through the serial interface or parallel
interface.
The font data in the CGROM can be changed by mask option.
Since the MSM9000B-xx has an LCD driving bias generator circuit, LCD bias voltages can be
obtained by merely providing a required capacitance externally.
The MSM9000B-xx is applicable to a variety of LCD panels by controlling the contrast.
FEATURES
• Logic voltage(V
DD
): 2.5 to 3.3 V
• LCD driving voltage(V
BI
) : 3.0 to 5.5 V
• Low current consumption: 35
mA
max.(operating)
• Switchable between 8-bit serial interface and 8-bit parallel interface
• Contains a 16-dot common driver and a 60-dot segment driver
• Contains CGROM with character fonts of (5 x 7 dots) x 256
• Built-in bias voltage generator circuit
• Built-in contrast adjusting circuit
• Built-in 32.768 kHz crystal oscillator circuit
• Provided with 120 dot arbitrators
• 1/9 duty mode (1 line : characters, 2 lines : arbitrators)
1/16 duty mode (2 lines : characters, 2 lines : arbitrators)
• Character blink operation can be switched between all-character lighting-on mode and all-
character lighting-off mode.
• Package:
TCP mounting with 35 mm wide film ; Tin-plated (Product name : MSM9000B-xx AV-Z-xx)
Chip
(Product name : MSM9000B-xx)
xx indicates code number.
1/38
¡ Semiconductor
MSM9000B-xx
PIN DESCRIPTIONS
Number
of Pins
1
1
1
1
8
1
1
1
1
1
1
1
1
1
2
1
60
16
1
1
4
1
1
2
2
112
Function
CPU Interface
Symbol
CS
WR
RD
C/D
DB0-7
SI
SO
SHT
Type
I
I
I
I
I/O
I
O
I
I
O
I
I
I
I
I
I
O
O
—
—
—
—
—
—
—
Description
Chip select input signal
Write enable signal, latch for serial interface
Read enable signal
Command/Data select input signal
8-bit parallel data inputs/outputs
Serial data input
Serial data output
Shift clock input for data input in serial interface mode
Crystal oscillation input, clock input
Crystal oscillation output
Parallel/Serial interface switching signal input
Duty select signal input
Clock select signal input
Reset is performed by setting the
RESET
input to "L"
level
Contrast control signal input
Test signal input. Fix to "L" Level or leave open
Segment outputs for LCD driving
Common outputs for LCD driving
Positive + power supply pin for LOGIC
GND pin
Boosted voltage output pins & bias power supply pins
Voltage multiplier output pin (3-/2-fold)
Haver output pin
Voltage multiplier (3-/2-fold)
Voltage multiplier (4-fold)
Oscillation
Control Signal
XT
XT
P/S
9D/16D
32K/EXT
RESET
N1, N2
TEST
LCD Driving
Output
Power Supply
SEG1-SEG60
COM1-COM16
V
DD
V
SS
V
SS1
, V
SS2
,
3
V
SS4
, V
SS5
V
SS6
V
SH
V
C1
, V
CC1
V
C2
, V
CC2
Total
4/38
¡ Semiconductor
MSM9000B-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Bias voltage
Input voltage
Storage temperature
Symbol
V
DD
V
BI
V
I
T
STG
Condition
Ta=25°C, V
DD
–V
SS
Ta=25°C, V
DD
–V
SS5
Ta=25°C
Chip
TCP
Rating
–0.3 to +4.6
–0.3 to +7
–0.3 to V
DD
+ 0.3
–55 to +150
–30 to +85
Unit
V
V
V
°C
Applicable pin
V
DD
, V
SS
V
DD
, V
SS5
All input pins
—
Ta: Ambient temperature
RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Bias voltage
IC source oscillation
Operating temperature
Symbol
V
DD
V
BI
f
int
T
op
Condition
V
DD
–V
SS
*1, V
DD
–V
SS5
*2
—
Range
2.5 to 3.3
3 to 5.5
26 to 47
–30 to +85
Unit
V
V
kHz
°C
Applicable pin
V
DD
, V
SS
V
DD,
V
SS5
*3
—
*1 V
DD
is the highest pin and V
SS5
the lowest for the bias voltage.
*2 Connect the specified capacitors to the voltage doubler and LCD bias generator.
*3 Make sure that the crystal oscillation frequency or the divided clock frequency falls within
this range.
Note 1: Ensure the chip is not exposed to any light.
Note 2: The bias voltage may exceed 5.5 V at some contrast stages. Adjust the stage with
software so that the bias voltage does not exceed 5.5 V.
5/38
京公网安备 11010802033920号
EEWORLD
