INTEGRATED CIRCUITS
DATA SHEET
TDA8060ATS
Satellite ZERO-IF QPSK
down-converter
Product specification
File under Integrated Circuits, IC02
2000 Nov 10
Philips Semiconductors
Product specification
Satellite ZERO-IF QPSK down-converter
FEATURES
•
Direct conversion Quadrature Phase Shift Keying
(QPSK) demodulation (Zero IF)
•
920 to 2200 MHz range
•
On-chip loop-controlled 0 or 90° phase shifter
•
Variable gain on RF input
•
60 MHz, at
−3
dB, bandwidth for baseband
I and Q amplifiers
•
Local oscillator output to PLL satellite or terrestrial
•
5 V supply voltage.
APPLICATIONS
•
Direct Broadcasting Satellite (DBS) QPSK
demodulation
•
Digital Video Broadcasting (DVB) QPSK demodulation.
GENERAL DESCRIPTION
TDA8060ATS
The direct conversion QPSK demodulator is the front-end
receiver dedicated to digital TV broadcasting, satisfying
both DVB and DBS TV standards.
The 920 to 2200 MHz wide range oscillator covers
American, European and Asian satellite bands as well as
the SMA-TV US standard.
Accurate QPSK demodulation is ensured by the on-chip
loop-controlled phase shifter. The Zero-IF concept
discards traditional IF filtering and intermediate conversion
techniques. It also simplifies the signal path.
The baseband I and Q signal bandwidth only depends, to
a certain extent, on the external filter used in the
application.
Optimum signal level is guaranteed by a gain-controlled
amplifier at the RF input. The pin AGC sets the gain for
both I and Q channels, providing a 37 dB range.
The chip also offers a selectable internal LO prescaler
(divide-by-2) and buffer that has been designed to be
compatible with the input of a terrestrial or satellite
frequency synthesizer.
QUICK REFERENCE DATA
SYMBOL
V
CC
∆Φ
f
osc
V
o(p-p)
T
amb
supply voltage
quadrature error
oscillator frequency
output voltage (peak-to-peak value)
ambient temperature
PARAMETER
MIN.
4.75
−
920
−
−20
TYP.
5.00
−
−
1
−
MAX.
5.25
3
2200
−
+85
UNIT
V
deg
MHz
V
°C
ORDERING INFORMATION
TYPE
NUMBER
TDA8060ATS
PACKAGE
NAME
SSOP24
DESCRIPTION
plastic shrink small outline package; 24 leads; body width 5.3 mm
VERSION
SOT340-1
2000 Nov 10
2
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BLOCK DIAGRAM
2000 Nov 10
LOW-PASS
FILTER
VCC(LO)
LOGND
18
22
21
15
14
IOUT
IBBIN
17
VCC(DIV) DIVGND
8
7
Philips Semiconductors
handbook, full pagewidth
VCC(MIX) MIXGND VCC(RF) RFGND
2
4
CONVERSION STAGE
I CONVERTER
13
IBBOUT
×
SYM
100 MHz
ASYM
AMP
Q CONVERTER
RFA 6
RFB 5
LNA
BASEBAND
STAGE
AMP
12
QBBOUT
AGC 1
SYM
100 MHz
ASYM
Satellite ZERO-IF QPSK down-converter
3
STABILIZED LO
PLL AND
AMPLIFIER
×
QUADRATURE
GENERATOR
TDA8060ATS
OSCILLATOR
9
VCC(BB)
PEN
3
DIVIDE-BY-2
16
10
11
QOUT QBBIN
LOW-PASS
FILTER
BBGND
24
LOOUTC
TKA
TKB
23
19
20
FCE411
LOOUT
TDA8060ATS
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Satellite ZERO-IF QPSK down-converter
PINNING
SYMBOL
AGC
V
CC(MIX)
PEN
MIXGND
RFB
RFA
RFGND
V
CC(RF)
V
CC(BB)
QOUT
QBBIN
QBBOUT
IBBOUT
IBBIN
IOUT
BBGND
V
CC(LO)
LOGND
TKA
TKB
DIVGND
V
CC(DIV)
LOOUTC
LOOUT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION
RF amplifier gain control input
supply voltage for mixer circuit (5 V)
prescaler enable
ground for mixer circuit
RF signal input B
RF signal input A
ground for RF circuit
supply voltage for RF circuit (5 V)
supply voltage for baseband circuit
(5 V)
‘Q’ output from demodulator
‘Q’ baseband amplifier input
‘Q’ baseband amplifier output
‘I’ baseband amplifier output
‘I’ baseband amplifier input
‘I’ output from demodulator
ground for baseband circuit
supply voltage for local oscillator
circuit (5 V)
ground for local oscillator circuit
tank circuit input A
tank circuit input B
ground for divider circuit
supply voltage for divider circuit
(5 V)
local oscillator output to synthesizer
divided or not according to
PEN voltage
MIXGND 4
RFB 5
RFA 6
handbook, halfpage
TDA8060ATS
AGC 1
VCC(MIX) 2
PEN 3
24 LOOUT
23 LOOUTC
22 VCC(DIV)
21 DIVGND
20 TKB
19 TKA
TDA8060ATS
RFGND 7
VCC(RF) 8
VCC(BB) 9
QOUT 10
QBBIN 11
QBBOUT 12
FCE412
18 LOGND
17 VCC(LO)
16 BBGND
15 IOUT
14 IBBIN
13 IBBOUT
Fig.2 Pin configuration.
2000 Nov 10
4
Philips Semiconductors
Product specification
Satellite ZERO-IF QPSK down-converter
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
V
CC
V
i(max)
t
sc(max)
T
amb
T
stg
T
j
HANDLING
supply voltage
maximum input voltage on all pins
maximum short-circuit time
ambient temperature
storage temperature
junction temperature
PARAMETER
MIN.
−0.3
−0.3
−
−20
−55
−
TDA8060ATS
MAX.
+6.0
V
CC
10
+85
+150
150
V
V
s
°C
°C
°C
UNIT
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
R
th(j-a)
PARAMETER
thermal resistance from junction to ambient
CONDITIONS
in free air
VALUE
120
UNIT
K/W
DC CHARACTERISTICS
V
CC
= 4.75 to 5.25 V; T
amb
=
−20
to +85
°C;
unless otherwise specified.
SYMBOL
V
CC
I
CC
PARAMETER
supply voltage
supply current
PEN = 5 V
PEN = 0 V
Conversion stage
V
I(RFA)
V
I(RFB)
V
O(IOUT)
V
O(QOUT)
V
O(LOOUT)
V
O(LOOUTC)
V
I(IBBIN)
V
I(QBBIN)
V
O(IBBOUT)
V
O(QBBOUT)
DC input voltage on pin RFA
DC input voltage on pin RFB
DC output voltage on pin IOUT
DC output voltage on pin QOUT
−
−
−
−
−
−
−
−
−
−
0.9
0.9
1.85
1.85
−
−
−
−
−
−
−
−
−
−
V
V
V
V
CONDITIONS
MIN.
4.75
73
70
TYP.
5.00
83
80
MAX.
5.25
93
90
V
mA
mA
UNIT
Quadrature generator
DC output voltage on pin LOOUT
DC output voltage on pin LOOUTC
4.0
4.0
V
V
Baseband stage
DC input voltage on pin IBBIN
DC input voltage on pin QBBIN
DC output voltage on pin IBBOUT
DC output voltage on pin QBBOUT
2.5
2.5
2.5
2.5
V
V
V
V
2000 Nov 10
5
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