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74F652SPC

Description
F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
Categorylogic    logic   
File Size76KB,8 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74F652SPC Overview

F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24

74F652SPC Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeDIP
package instruction0.300 INCH, PLASTIC, MS-001, DIP-24
Contacts24
Reach Compliance Codecompli
Is SamacsysN
Other featuresWITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
Control typeINDEPENDENT CONTROL
Counting directionBIDIRECTIONAL
seriesF/FAST
JESD-30 codeR-PDIP-T24
JESD-609 codee3
length31.915 mm
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
MaximumI(ol)0.064 A
Number of digits8
Number of functions1
Number of ports2
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT APPLICABLE
power supply5 V
Maximum supply current (ICC)150 mA
Prop。Delay @ Nom-Su7.5 ns
propagation delay (tpd)9 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT APPLICABLE
translateN/A
Trigger typePOSITIVE EDGE
width7.62 mm
Base Number Matches1
74F651 • 74F652 Transceivers/Registers
March 1988
Revised August 1999
74F651 • 74F652
Transceivers/Registers
General Description
These devices consist of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function.
Features
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data
s
Choice of non-inverting and inverting data paths
74F651 inverting
74F652 non-inverting
Ordering Code:
Order Number
74F651SC
74F651SPC
74F652SC
74F652SPC
Package Number
M24B
N24C
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 1999 Fairchild Semiconductor Corporation
DS009581
www.fairchildsemi.com

74F652SPC Related Products

74F652SPC 74F652SC 74F651 74F651SC 74F651SPC
Description F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
Counting direction BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL
series F/FAST F/FAST F/FAST F/FAST F/FAST
length 31.915 mm 15.4 mm 15.4 mm 15.4 mm 31.915 mm
Number of digits 8 8 8 8 8
Number of functions 1 1 1 1 1
Number of ports 2 2 2 2 2
Number of terminals 24 24 24 24 24
Maximum operating temperature 70 °C 70 °C 70 Cel 70 °C 70 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE INVERTED INVERTED
surface mount NO YES YES YES NO
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE GULL WING GULL WING GULL WING THROUGH-HOLE
Terminal location DUAL DUAL DUAL DUAL DUAL
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 7.62 mm 7.5 mm 7.5 mm 7.5 mm 7.62 mm
Is it Rohs certified? conform to conform to - incompatible incompatible
Maker Fairchild Fairchild - Fairchild Fairchild
Parts packaging code DIP SOIC - SOIC DIP
package instruction 0.300 INCH, PLASTIC, MS-001, DIP-24 0.300 INCH, MS-013, SOIC-24 - 0.300 INCH, MS-013, SOIC-24 0.300 INCH, PLASTIC, MS-001, DIP-24
Contacts 24 24 - 24 24
Reach Compliance Code compli compli - compli unknow
Is Samacsys N N - N N
Other features WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION - WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
Control type INDEPENDENT CONTROL INDEPENDENT CONTROL - INDEPENDENT CONTROL INDEPENDENT CONTROL
JESD-30 code R-PDIP-T24 R-PDSO-G24 - R-PDSO-G24 R-PDIP-T24
JESD-609 code e3 e3 - e0 e0
Logic integrated circuit type REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER - REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
MaximumI(ol) 0.064 A 0.064 A - 0.064 A 0.064 A
Package body material PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP SOP - SOP DIP
Encapsulate equivalent code DIP24,.3 SOP24,.4 - SOP24,.4 DIP24,.3
Package shape RECTANGULAR RECTANGULAR - RECTANGULAR RECTANGULAR
Package form IN-LINE SMALL OUTLINE - SMALL OUTLINE IN-LINE
Peak Reflow Temperature (Celsius) NOT APPLICABLE 260 - NOT SPECIFIED NOT SPECIFIED
power supply 5 V 5 V - 5 V 5 V
Maximum supply current (ICC) 150 mA 150 mA - 150 mA 150 mA
Prop。Delay @ Nom-Su 7.5 ns 7.5 ns - 9 ns 9 ns
propagation delay (tpd) 9 ns 9 ns - 9 ns 9 ns
Certification status Not Qualified Not Qualified - Not Qualified Not Qualified
Maximum seat height 5.08 mm 2.65 mm - 2.65 mm 5.08 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V - 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V - 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V - 5 V 5 V
technology TTL TTL - TTL TTL
Terminal surface Matte Tin (Sn) Matte Tin (Sn) - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal pitch 2.54 mm 1.27 mm - 1.27 mm 2.54 mm
Maximum time at peak reflow temperature NOT APPLICABLE NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
translate N/A N/A - N/A N/A
Base Number Matches 1 1 - 1 1
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