• Eliminates the need for external crystal oscillator.
• Internal PLL to generate up to 125-MHz output.
• Suitable for most PC, consumer and networking
applications.
• Application compatibility in standard and low-power
systems.
• CY25701 can be used as a direct replacement in 3.3V
applications if Spread Spectrum Clock (SSC) is
required for EMI reduction without any PCB
modification.
• In-house programming of samples and prototype
quantities is available using the CY3672 programming
kit and CY36xx socket adapter. Sample and production
quantities are available through Cypress’s value-added
distribution partners.
Logic Block Diagram
Pin Configuration
CY25702
4-pin Plastic SMD
RFB
PLL
1
C
XIN
PROGRAMMABLE
CONFIGURATION
C
XOUT
OUTPUT
DIVIDERS
and
MUX
OE/PD#
VSS
VDD 4
CLK 3
3
CLK
2
1
OE/PD#
4
VDD
2
VSS
Cypress Semiconductor Corporation
Document #: 38-07721 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised March 11, 2005
CY25702
Pin Definition
Pin
1
2
3
4
OE/PD#
VSS
CLK
VDD
Name
Description
Output Enable pin: Active HIGH.
If OE = 1, CLK is enabled.
Power Down pin: Active LOW.
If PD# = 0, Power Down is enabled.
Power supply ground.
Clock output.
3.3V or 5.0V power supply.
Table 1. Programming Data Requirement
Pin Function
Pin Name
Pin#
Units
Program Value
Output Frequency
CLK
3
MHz
ENTER DATA
Output Enable/Power Down
OE/PD#
1
N/A
ENTER DATA
Power Supply
VDD
4
V
ENTER DATA
Functional Description
The CY25702 is a Crystal Oscillator (XO).
The device uses a Cypress proprietary PLL to synthesize the
frequency of the embedded input crystal.
The CY25702 uses a programmable configuration memory
array to synthesize output frequency.
The frequency CLK output can be programmed from
10–125 MHz.
The CY25702 is available in a 4-pin plastic SMD packages
with operating temperature range of –20 to 70°C.
Additional information on the CY25702 can be obtained from
the Cypress web site at www.cypress.com.
Output Frequency, CLK Output (CLK, pin 3)
The frequency at the CLK output is produced by synthesizing
the embedded crystal oscillator frequency input. The range of
synthesized clock is from 1–125 MHz when V
DD
= 5V and
1–90 MHz when V
DD
= 3.3V.
Output Enable or Power Down (OE/PD#, pin 1)
Pin 1 can be programmed as either output enable (OE) or
Power Down (PD#).
Programming Description
Field/Factory-Programmable CY25702
Field/Factory programming is available for samples and
manufacturing by Cypress and its distributors. All requests
must be submitted to the local Cypress Field Application
Engineer (FAE) or sales representative. Once the request has
been processed, you will receive a new part number, samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.
Absolute Maximum Rating
Supply Voltage (V
DD
)......................................–0.5V to +7.0V
DC Input Voltage ................................... –0.5V to V
DD
+ 0.5V
Storage Temperature (Non-condensing) .... –55°C to +100°C
Junction Temperature ................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Operating Conditions
Parameter
V
DD1
V
DD2
T
A
C
LOAD
F
CLK1
F
CLK2
T
PU
Description
Supply Voltage Range
Supply Voltage Range
Ambient Temperature
Max. Load Capacitance @ pin 3
CLK output frequency, C
LOAD
= 15 pF, V
DD
= 5.0V
CLK output frequency, C
LOAD
= 15 pF, V
DD
= 3.3V
Power-up time for VDD to reach minimum specified
voltage (power ramp must be monotonic)
Min.
3.00
4.50
–20
–
1.0
1.0
0.05
Typ.
3.30
5.00
–
–
–
–
–
Max.
3.60
5.50
70
15
125
90
500
Unit
V
V
°C
pF
MHz
MHz
ms
Document #: 38-07721 Rev. *A
Page 2 of 7
CY25702
DC Electrical Characteristics
Parameter
V
OH1
V
OL1
V
OH2
V
OL2
V
IH1
V
IL1
V
IH2
V
IL2
I
IH
I
IL
I
OZ
C
IN
I
VDD1
I
VDD2
I
VDD3
I
VDD4
I
PD#
FS
AG
SR
Description
High Output Voltage
Low Output Voltage
High Output Voltage
Low Output Voltage
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Current (pin 1)
Input Low Current (pin 1)
Input Capacitance (pin 1)
Supply Current
Supply Current
Supply Current
Supply Current
Power Down Current
Frequency Stability
Aging
Shock Resistance
Condition
V
DD
= 5.0V, I
OH
= –16 mA
V
DD
= 5.0V, I
OL
= 16 mA
V
DD
= 3.3V, I
OH
= –8 mA
V
DD
= 3.3V, I
OL
= 8 mA
V
DD
= 5.0V
V
DD
= 5.0V
V
DD
= 3.3V
V
DD
= 3.3V
V
in
= V
DD
V
in
= V
SS
Pin 1, OE or PD#
V
DD
= 3.3V, CLK = 1 to 90 MHz,
C
LOAD
= 0, OE = V
DD
V
DD
= 3.3V, CLK = 1 to 90 MHz,
C
LOAD
= 0, OE = GND
V
DD
= 5.0V, CLK = 1 to 125 MHz,
C
LOAD
= 0, OE = V
DD
V
DD
= 5.0V, CLK = 1 to 125 MHz,
C
LOAD
= 0, OE = GND
PD# = GND
–20 to +70°C
Ta = 25°C, First Year
Three drops on a hard board from 750 mm or
excitation test with 29.400m/s
2
x 0.3ms x 1/2
sinewave in three directions
Min.
V
DD
– 0.4
–
V
DD
– 0.4
–
2.0
–
0.7V
DD
–
–
–
–10
–
–
–
–
–
–
–50
–5
–20
Typ.
–
–
–
–
–
–
–
–
–
–
–
5
–
–
–
–
–
–
–
–
Max.
–
0.4
–
0.4
–
0.8
–
0.2V
DD
10
10
10
7
28
16
45
30
50
50
5
20
Unit
V
V
V
V
V
V
V
V
µA
µA
µA
pF
mA
mA
mA
mA
µA
ppm
ppm
ppm
Output Leakage Current (pin 3) Three-state output, OE = 0
AC Electrical Characteristics
Parameter
DC
t
R
t
F
T
OE1
T
OE2
T
LOCK
T
SU
T
PDD
t
J1
t
J2
Description
Output Duty Cycle
Output Rise Time
Output Fall Time
Condition
CLK, Measured at V
DD
/2
20%–80% of V
DD,
C
L
= 15 pF
20%–80% of V
DD,
C
L
= 15 pF
Min.
40
–
–
–
–
–
–
–
–
–
–
Typ.
50
–
–
150
150
–
–
–
–
–
–
Max.
60
4.0
4.0
350
350
10
5
25
200
150
200
Unit
%
ns
ns
ns
ns
ms
ms
ns
ps
ps
ps
Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped
outputs (Asynchronous)
Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a
valid frequency (Asynchronous)
PLL Lock Time
Power Down Delay Time
Cycle-to-cycle jitter
V
DD
= 3.3V
Cycle-to-cycle jitter
V
DD
= 5.0V
Time for CLK to reach valid frequency
PD# pin Low to CLK Low (Asynchronous)
1.0 MHz
≤
fo
≤
125 MHz, C
L
= 15 pF
33 MHz
≤
fo
≤
125 MHz, C
L
= 15 pF
1.0 MHz
≤
fo
≤
33 MHz, C
L
= 15 pF
Start-up time out of Power Down PD# pin Low to High
Document #: 38-07721 Rev. *A
Page 3 of 7
CY25702
Application Circuit
Power
VDD
1 OE/PD#
VDD 4
0.1uF
CLK 3
(GND if PD#)
CY25702
2 VSS
Switching Waveforms
Duty Cycle Timing (DC = t
1A
/t
1B
)
CLK
t
1A
t
1B
Output Rise/Fall Time
CLK
Tr
Tf
Output Rise time (Tr) = 20 to 80% of V
DD
Output Fall time (Tf) = 80 to 20% of V
DD
V
DD
0V
Output Enable/Disable Timing
OUTPUT
ENABLE
V
DD
0V
V
IL
V
IH
T
OE2
CLK
T
OE1
High Impedance
Document #: 38-07721 Rev. *A
Page 4 of 7
CY25702
Ordering Information
Part Number
[1,2]
CY25702JXCZZZZ
CY25702JXCZZZZT
CY25702FJXC
CY25702FJXCT
CY25702XCZZZ
CY25702XCZZZT
CY25702FXC
CY25702FXCT
Package description
4-Lead Plastic JE04A SMD – Lead-free
4-Lead Plastic JE04A SMD, Tape and Reel – Lead-free
4-Lead Plastic JE04A SMD – Lead-free
4-Lead Plastic JE04A SMD, Tape and Reel – Lead-free
4-Lead Plastic JE04B SMD – Lead-free
4-Lead Plastic JE04B SMD, Tape and Reel – Lead-free
4-Lead Plastic JE04B SMD – Lead-free
4-Lead Plastic JE04B SMD, Tape and Reel – Lead-free
Product Flow
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Commercial, –20° to 70°C
Package Drawings and Dimensions
4-Lead JEC JE04A
10.2±0.3
(10.5 MAX)
4
1.0±0.2
(1.0)
5.0
5.6±0.2
(5.8 MAX)
3.6
1.0±0.2
(1.0)
1
1.3
2.1
2.4
2.5
-0.1
(2.7 MAX)
+0.2
4.6
0.1
0.51
0.15±0.1
(0.05 MIN)
5.08±0.1
DIMENSIONS IN MILLIMETERS
REFERENCE JEDEC: N/A
PKG. WEIGHT: 0.24 gms
5.08
RECOMMENDED SOLDERING PATTERN
51-85204-*A
Notes:
1. “ZZZZ” or “ZZZ” denotes the assigned product dash number. This number will be assigned by factory after the output frequency and spread percent programming
data is received from the customer.
2. “FJXC” or “FX” suffix is used for products programmed in field by Cypress distributors.
京公网安备 11010802033920号
EEWORLD
