PD-97051A
iP2003APbF
Synchronous Buck
Multiphase Optimized LGA Power Block
Features:
Integrated Power Semiconductors, Drivers & Passives
Full function multiphase building block
Output current 40A continuous with no derating up to
T
PCB
= 100°C and T
CASE
= 100°C
Operating frequency up to 1.0 MHz
Proprietary packaging enables ultra low Rth
j-case top
Efficient dual sided cooling
Small footprint low profile (9mm x11mm x 2.2mm) package
Optimized for very low power losses
LGA interface
Ease of design
iP2003APbF Power Block
Description
The iP2003APbF is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 9mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM
controller, the output inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
Pin #
1
iP2003APbF Internal Block Diagram
V
SWS1
V
SWS2
Pin N am e
Pin Function
V
DD
Supply voltage for the internal circuitry.
2
ENA BLE
W hen set to logic level high, internal circuitry
of the device is enabled. W hen set to logic
level low, the PRD Y pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current reduces to 10µ A.
T T L-level input signal to M OSFET drivers.
Power Ready - This pin indicates the status of
EN AB LE or V
D D
. T his output will be driven
low when EN ABLE is logic low or when V
D D
is less than 4.4V (typ.). W hen EN AB LE is
logic high and V
D D
is greater than 4.4V (typ.),
this output is driven high. T his output has a
10mA source and 1mA sink capability.
Power G round - connection to the ground of
bulk and filter capacitors.
Switching N ode - connection to the output
inductor.
Input voltage pin. External bypass ceramic
capacitors must be added directly next to the
block.
Floating pin. For internal use. E xternally, short
to V
SW S2
pin only
.
Floating pin. For internal use. E xternally, short
to V
SW S1
pin only
.
V
IN
PRDY
ENABLE
PWM
V
DD
MOSFET
Driver with
dead time
control
3
PW M
V
SW
4
PRD Y
PGND
5, 7
6
PG ND
V
SW
V
IN
V
SW S1
V
SW S2
PACKAGE
DESCRIPTION
INTERFACE
CONNECTION
PARTS
PER BAG
PARTS
PER
REEL
T&R
ORIENTATION
8
9
iP2003APbF
iP2003ATRPbF
LGA
LGA
10
---
---
1000
Fig 12
10
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8/16/06
1
iP2003APbF
V
DD
to PGND
PWM to PGND
Enable to PGND
Output RMS Current
All specifications @25°C (unless otherwise specified)
Min
-
-
-0.3
-0.3
-
Typ
-
-
-
-
-
Max
16
6.0
V
DD
+0.3
V
DD
+0.3
40
Units
V
V
V
V
A
Not to exceed 6.0V
Not to exceed 6.0V
Measured at V
SW
Conditions
Absolute Maximum Ratings:
Parameter
Symbol
V
IN
to PGND
V
IN
V
DD
PWM
ENABLE
I
OUT
Recommended Operating Conditions:
Min
Parameter
Symbol
Supply Voltage
Input Voltage
Output Voltage
Output Current
Operating Frequency
Operating Duty Cycle
Block Temperature
V
DD
V
IN
V
OUT
I
OUT
fsw
D
T
BLK
4.6
3.0
0.8
-
300
-
-40
Typ
5.0
-
-
-
-
-
-
Max
5.5
13.2
3.3
40
1000
85
125
Units
V
V
V
A
kHz
%
°C
Conditions
Electrical Specifications @ V
DD
= 5V (unless otherwise specified):
Parameter
Symbol
Min
Typ
Max
Units
P
LOSS
Block Power Loss
c
-
9.4
11.7
W
Turn On Delay
d
Turn Off Delay
d
V
IN
Quiescent Current
V
DD
Quiescent Current
Under-Voltage Lockout
Start Threshold
Hysteresis
Enable
Input Voltage High
Input Voltage Low
Power Ready
Logic Level High
Logic Level Low
PWM Input
Logic Level High
Logic Level Low
t
d(on)
t
d(off)
I
Q-VIN
I
Q-VDD
UVLO
V
START
V
Hvs-UVLO
ENABLE
V
IH
V
IL
PRDY
V
OH
V
OL
PWM
V
OH
V
OL
-
-
-
-
4.2
-
2.1
-
4.5
-
2.1
-
63
26
-
10
4.4
150
-
-
4.6
0.1
-
-
-
-
1.0
-
4.5
-
-
0.8
-
0.2
-
0.8
V
V
ns
mA
µA
V
mV
V
Conditions
V
IN
=12V, V
OUT
=1.3V
I
OUT
=40A, f
SW
=1MHz
L = 0.3µH
Enable = 0V, V
IN
=12V
Enable = 0V, V
DD
=5V
V
DD
=4.6V, I
Load
=10mA
V
DD
<UVLO Threshold, I
Load
= 1mA
Measurement made using six 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see
2
Fig. 8).
Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
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iP2003APbF
16
14
12
Power Loss (W)
VIN = 12V
VOUT = 1.3V
f sw
L
= 1MHz
= 0.30µH
T BLK = 125°C
10
8
6
4
2
0
0
5
10
15
20
Output Current (A)
Maximum
Typical
25
30
35
40
Fig. 1:
Power Loss vs. Current
Case Temperature (°C)
0
40
36
32
Output Current (A)
10
20
30
40
50
60
70
80
90
100
110
120
130
28
24
20
16
12
8
4
0
0
10
20
30
VIN = 12V
VOUT = 1.3V
f sw
L
= 1MHz
= 0.30µH
Safe
Operating
Area
Tx
40
50
60
70
80
90
100
110
120
130
PCB Temperature (°C)
Fig. 2:
Safe Operating Area (SOA) vs. T
PCB
& T
CASE
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3
iP2003APbF
Typical Performance Curves
1.28
1.24
Power Loss (Normalized)
Power Loss (Normalized)
VOUT = 1.3V
I OUT = 40A
f sw
= 1MHz
L
= 0.3µH
T BLK = 125°C
7
6
5
4
3
2
1
0
-1
SOA Temp Adjustment (°C)
1.16
1.12
1.08
1.04
1.00
0.96
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
Output Voltage (V)
VIN = 12V
I OUT = 40A
f sw
= 1MHz
L
= 0.30µH
T BLK = 125°C
4.0
SOA Temp Adjustment (°C)
1.20
1.16
1.12
1.08
1.04
1.00
0.96
3
4
5
6
7
8
9
3.0
2.0
1.0
0.0
-1.0
10
11
12
13
Input Voltage (V)
Fig. 3:
Normalized Power Loss vs. V
IN
1.05
Power Loss (Normalized)
Fig. 4:
Normalized Power Loss vs. V
OUT
1
Power Loss (Normalized)
1.06
SOA Temp Adjustment (°C)
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
200
VIN = 12V
VOUT = 1.3V
IOUT = 40A
L = 0.30µH
TBLK = 125°C
0
-1
-2
-3
-4
-5
-6
-7
1.04
VIN = 12V
VOUT = 1.3V
I OUT = 40A
f sw
= 1MHz
T BLK = 125°C
1.5
SOA Temp Adjustment (°C)
1.0
1.02
0.5
1.00
0.0
0.98
0.1
0.3
0.5
0.7
0.9
Output Inductance (µH)
-0.5
300
400
500
600
700
800
900 1000
Switching Frequency (kHz)
Fig. 5:
Normalized Power Loss vs. Frequency
100
90
Average IDD (mA)
80
70
60
50
40
300
400
500
600
700
Fig. 6:
Normalized Power Loss vs. Inductance
Does not include
PRDY current
TBLK = 25°C
800
900
1000
Switching Frequency (kHz)
4
Fig. 7:
I
DD
(V
DD
current) vs. Frequency
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iP2003APbF
Applying the Safe Operating Area (SOA) Curve
The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum
current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn
out through the printed circuit board and the top of the case.
Procedure
1) Draw a line from Case Temp axis at T
CASE
to the PCB
Temp axis at T
PCB
.
2) Draw a vertical line from the T
X
axis intercept to the SOA
curve.
3) Draw a horizontal line from the intersection of the vertical
line with the SOA curve to the Y-axis. The point at which
the horizontal line meets the Y-axis is the SOA current.
Output Current (A)
Case Temperature (ºC
)
0
10
20
30
40
50
60
70
80
90
100
110
120
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
110
120
T
X
Safe
Operating
Area
V
IN
= 12V
V
OUT
= 1.3V
f
SW
= 1MHz
L=0.3uH
PCB Temperature (ºC)
Calculating Power Loss and SOA for Different Operating Conditions
To calculate power loss for a given set of operating conditions, the following procedure should be followed:
Determine the maximum current for each iP2003APbF and obtain the maximum power loss from Fig 1. Use the curves
in Figs. 3, 4, 5 and 6 to obtain normalized power loss values that match the operating conditions in the application. The
maximum power loss under the operating conditions is then the product of the power loss from Fig. 1 and the normal-
ized values.
To calculate the SOA for a given set of operating conditions, the following procedure should be followed:
Determine the maximum PCB temperature and Case temperature at the maximum operating current of each
iP2003APbF. Obtain the SOA temperature adjustments that match the operating conditions in the application from
Figs. 3, 4, 5 and 6. Then, add the sum of the SOA temperature adjustments to the Tx axis intercept in Fig 2.
The example below explains how to calculate maximum power loss and SOA.
Example:
Operating Conditions
Output Current = 40A
Sw Freq= 900kHz
Calculating Maximum Power Loss:
(Fig. 1)
(Fig. 3)
(Fig. 4)
(Fig. 5)
(Fig. 6)
Maximum power loss
=
15W
Normalized power loss for input voltage
≈
0.98
Normalized power loss for output voltage
≈
1.14
Normalized power loss for frequency
≈
0.94
Normalized power loss for inductor value
≈
1.013
Input Voltage = 10V
Inductor = 0.2µH
Output Voltage = 3.3V
T
PCB
= 100°C, T
CASE
= 110°C
Calculated Maximum Power Loss for given conditions = 15W x 0.98 x 1.14 x 0.94 x 1.013
≈
15.96W
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