USB1T1102 • USB1T1102R (Preliminary) Universal Serial Bus Peripheral Transceiver with Voltage Regulator
August 2004
Revised August 2004
USB1T1102 • USB1T1102R (Preliminary)
Universal Serial Bus Peripheral Transceiver
with Voltage Regulator
General Description
This chip provides a USB Transceiver functionality with a
voltage regulator that is compliant to USB Specification
Rev 2.0. this integrated 5V to 3.3V regulator allows inter-
facing of USB Application specific devices with supply volt-
ages ranging from 1.65V to 3.6V with the physical layer of
Universal Serial Bus. It is capable of operating at 12Mbits/s
(full speed) data rates and hence is fully compliant to USB
Specification Rev 2.0. The Vbusmon pin allows for monitor-
ing the Vbus line.
The USB1T1102 also provides exceptional ESD protection
with 15kV contact HBM on D
+
, D
−
pins.
Features
s
Complies with Universal Serial Bus Specification 2.0
s
Integrated 5V to 3.3V voltage regulator for powering
VBus
s
Utilizes digital inputs and outputs to transmit and receive
USB cable data
s
Supports full speed (12Mbits/s) data rates
s
Ideal for portable electronic devices
s
MLP technology package (16 pin) with HBCC footprint
s
15kV contact HBM ESD protection on bus pins
Ordering Code:
Order Number
USB1T1102MPX
USB1T1102RMPX
(Preliminary)
USB1T1102MHX
USB1T1102RMHX
(Preliminary)
Package Number
MLP14D
MLP14D
MLP16HB
MLP16HB
Package Description
14-Terminal Molded Leadless Package (MLP), 2.5mm Square
14-Terminal Molded Leadless Package (MLP), 2.5mm Square
16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square
16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square
Logic Diagram
Note:
On the USB1T1102R the 1.5k resistor is integrated into the part, and connects V
PU
and D+ eliminating the need for this external pull-up resistor.
© 2004 Fairchild Semiconductor Corporation
DS500877
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USB1T1102 • USB1T1102R (Preliminary)
Connection Diagrams
MLP16 GND Exposed Diepad
MLP14 GND Exposed Diepad
(Bottom View)
(Bottom View)
Terminal Descriptions
Terminal Number
MLP14
1
MLP16
1
Terminal
Name
OE
I/O
I
Terminal Description
Output Enable:
Active LOW enables the transceiver to transmit data on the bus. When not
active the transceiver is in the receive mode (CMOS level is relative to V
CCIO
)
Receive Data Output:
Non-inverted CMOS level output for USB differential Input (CMOS output level
is relative to V
CCIO
). Driven LOW when SUSPN is HIGH; RCV output is stable
and preserved during SE0 condition.
Single-ended D
+
receiver output V
P
(CMOS level relative to V
CCIO
):
Used for external detection of SE0, error conditions, speed of connected device;
Pin also acts as drive data input V
po
(see Table 1 and Table 2).
Output drive is 4 mA buffer.
Single-ended D
−
receiver output V
m
(CMOS level relative to V
CCIO
):
Used for external detection of SE0, error conditions, speed of connected device;
Pin also acts as drive data input V
mo
(see Table 1 and Table 2).
Output drive is 4 mA buffer.
Suspend:
Enables a low power state (CMOS level is relative to V
CCIO
). While the
SUSPND pin is active (HIGH) it will drive the RCV pin to logic “0” state.
No Connect
Supply Voltage for digital I/O pins (1.65V to 3.6V):
When not connected the D
+
and D
−
pins are in 3-STATE. This supply bus is
totally independent of V
CC
(5V) and V
REG
(3.3V).
O
Vbus monitor output (CMOS level relative to V
CCIO
):
When Vbus
>
4.1V then Vbusmon
=
HIGH and when Vbus
<
3.6V then
Vbusmon
=
LOW. If SUSPND
=
HIGH then Vbusmon is pulled HIGH.
Data
+
, Data
−
:
Differential data bus conforming to the USB standard.
No Connect
No Connect
Internal Regulator Option:
Regulated supply output voltage (3.0V to 3.6V) during 5V operation;
decoupling capacitor of at least 0.1
µ
F is required.
Regulator ByPass Option:
Used as supply voltage input for 3.3V operation.
Internal Regulator Option:
Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB
line Vbus.
Regulator ByPass Option:
Connected to V
REG
(3.3V)
2
2
2
RCV
O
3
3
V
p
/V
po
I/O
4
4
V
m
/V
mo
I/O
5
5
SUSPND
I
—
6
6
7
NC
V
CCIO
7
8
Vbusmon
9, 8
10
—
11
10, 9
11
12
13
D
+
, D
−
NC
NC
V
REG
(3.3V)
AI/O
12
14
V
CC
(5.0V)
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USB1T1102 • USB1T1102R (Preliminary)
Terminal Descriptions
Terminal Number
MLP14
13
MLP16
15
Terminal
Name
V
PU
(3.3V)
(Continued)
I/O
Terminal Description
Pull-up Supply Voltage (3.3V
±
10%):
Connect an external 1.5k
Ω
resistor on D
+
(FS data rate);
Pin function is controlled by Config input pin:
Config
=
LOW
−
V
PU
(3.3V) is floating (High Impedance) for zero pull-up current.
Config
=
HIGH
−
V
PU
(3.3V)
=
3.3V; internally connected to V
REG
(3.3V).
14
16
Config
GND
I
GND
USB connect or disconnect software control input.
Configures 3.3V to external 1.5k
Ω
resistor on D
+
when HIGH.
GND supply down bonded to exposed diepad to be connected to the PCB GND.
Exposed Exposed
Diepad Diepad
Functional Description
The USB1T1102 transceiver is designed to convert CMOS
data into USB differential bus signal levels and to convert
USB differential bus signal to CMOS data.
To minimize EMI and noise the outputs are edge rate con-
trolled with the rise and fall times controlled and defined for
full speed data rates only (12Mbits/s). The rise, fall times
are balanced between the differential pins to minimize
skew.
The USB1T1102 differs from earlier USB Transceiver in
that the V
p
/V
m
and V
po
/V
mo
pins are now I/O pins rather
than discrete input and output pins. Table 1 describes the
specific pin functionality selection. Table 2 and Table 3
describe the specific Truth Tables for Driver and Receiver
operating functions.
The USB1T1102 also has the capability of various power
supply configurations to support mixed voltage supply
applications (see Table 4) and Section 2.1 for detailed
descriptions.
Functional Tables
TABLE 1. Function Select
SUSPND
L
L
H
H
OE
L
H
L
H
D
+
, D
−
Driving &
Receiving
Receiving
(Note 1)
Driving
3-STATE
(Note 1)
RCV
Active
Active
Inactive
(Note 2)
Inactive
(Note 2)
V
p
/V
po
V
po
Input
V
p
Output
V
po
Input
V
p
Output
V
m
/V
mo
V
mo
Input
Function
Normal Driving
(Differential Receiver Active)
V
m
Output Receiving
V
mo
Input
Driving during Suspend
(Differential Receiver Inactive)
V
m
Output Low Power State
Note 1:
Signal levels is function of connection and/or pull-up/pull-down resistors.
Note 2:
For SUSPND
=
HIGH mode the differential receiver is inactive and the output RCV is forced LOW. The out-of-suspend signaling (K) is detected via
the single-ended receivers of the V
p
/V
po
and V
m
/V
mo
pins.
TABLE 2. Driver Function (OE
=
L) using Differential Input Interface
V
m
/V
mo
L
L
H
H
Note 3:
SE0
=
Single Ended Zero
V
p
/V
po
L
H
L
H
TABLE 3. Receiver Function (OE
=
H)
D
+
, D
−
RCV
H
L
X
V
p
/V
po
H
L
L
Data
SE0 (Note 3)
Differential Logic 1
Differential Logic 0
Illegal State
V
m
/V
mo
L
H
L
Differential Logic 1
Differential Logic 0
SE0
X
=
Don’t Care
3
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USB1T1102 • USB1T1102R (Preliminary)
Power Supply Configurations and Options
The two modes of power supply operation are:
• Normal Mode: V
CCIO
and V
CC
(5V) are connected or
V
CCIO
, V
CC
(5V) and [V
REG
(3.3V) and V
CC
(5V) shorted
for Bypass mode]
1. For 5V operation V
CC
is connected to 5V source
(4.0V to 5.5V) and the internal voltage regulator then
produces 3.3V for the USB connections.
2. For 3.3V operation both V
CC
and V
REG
are con-
nected to a 3.3V source (3.0V to 3.6V)
In both cases for normal mode the V
CCIO
is an indepen-
dent voltage source (1.65V to 3.6V) that is a function of
the external circuit configuration.
• Sharing Mode: V
CCIO
is only supply connected. V
CC
and
V
REG
are not connected. In this mode the D
+
and D
−
pins are 3-STATE and the USB1T1102 allows external
signals up to 3.6V to share the D
+
and D
−
bus lines.
Internally the circuitry limits leakage from D
+
and D
−
pins (maximum 10
µ
A) and V
CCIO
such that device is in
low power (suspended) state. Pins Vbusmon and RCV
are forced LOW as an indication of this mode with Vbus-
mon being ignored during this state.
A summary of the Supply Configurations is described in
Table 4.
TABLE 4. Power Supply Configuration Options
Pins
V
CC
(5V)
Power Supply Mode Configuration
Sharing
Not Connected
Normal (Regulated Output)
Connected to 5V Source
Normal (Regulator Bypass)
Connected to V
REG
(3.3V)
[Max Drop of 0.3V]
(2.7V to 3.6V)
Connected to 3.3V Source
1.65V to 3.6V Source
3.3V Available if
Config
=
HIGH
Function of Mode Set Up
Function of Mode Set Up
Function of Mode Set Up
Function of Mode Set Up
Function of Mode Set Up
V
REG
(3.3V)
V
CCIO
V
PU
(3.3V)
D
+
, D
−
V
p
/V
po
, V
m
/V
mo
RCV
Vbusmon
OE, SUSPND, Config
Not Connected
1.65V to 3.6V Source
3-STATE (Off)
3-STATE
L
L
L
Hi-Z
3.3V, 300
µ
A
Regulated Output
1.65V to 3.6V Source
3.3V Available if
Config
=
HIGH
Function of Mode Set Up
Function of Mode Set Up
Function of Mode Set Up
Function of Mode Set Up
Function of Mode Set Up
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4
USB1T1102 • USB1T1102R (Preliminary)
ESD Protection
ESD Performance of the USB1T1102
HBM D
+
/D
−
: 15.0kV
HBM, all other pins (Mil-Std 883E): 6.5kV
ESD Protection: D
+
/D
−
Pins
Since the differential pins of a USB transceiver may be
subjected to extreme ESD voltages, additional immunity
has been included in the D
+
and D
−
pins without compro-
mising performance. The USB1T1102 differential pins have
ESD protection to the following limits:
• 15kV using the contact Human Body Model
• 8kV using the Contact Discharge method as specified in
IEC 61000-4-2
Human Body Model
Figure 1 shows the schematic representation of the Human
Body Model ESD event. Figure 2 is the ideal waveform rep-
resentation of the Human Body Model.
IEC 61000-4-2, IEC 60749-26 and IEC 60749-27
The IEC 61000-4-2 standard covers ESD testing and per-
formance of finished equipment, and as such evaluates the
equipment in its entirety for ESD immunity. Fairchild
Semiconductor has evaluated this device using the
IEC 6100-4-2 representative system model depicted in Fig-
ure 3. Under the additional standards set forth by the IEC,
this device is also compliant with IEC 60749-26 (HBM) and
IEC 60749-27 (MM).
Additional ESD Test Conditions
For additional information regarding our product test meth-
odologies and performance levels, please contact Fairchild
Semiconductor.
FIGURE 2. HBM Current Waveform
FIGURE 1. Human Body ESD Test Model
FIGURE 3. IEC 61000-4-2 ESD Test Model
5
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