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74LCX245

Description
LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20
Categorysemiconductor    logic   
File Size242KB,10 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric View All

74LCX245 Overview

LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20

74LCX245 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage2 V
Rated supply voltage2.7 V
Number of ports2
Processing package descriptionSOP-20
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingNICKEL PALLADIUM GOLD
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelMILITARY
seriesLVC/LCX/Z
Output characteristics3-ST
Logic IC typeTRANSCEIVER
Number of digits8
Output polarityTRUE
propagation delay TPD9.2 ns
74LCX245
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER(3-STATE)
WITH 5V TOLERAT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
PD
= 7.0 ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LCX245M
T&R
74LCX245MTR
74LCX245TTR
DESCRIPTION
The 74LCX245 is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
PIN CONNECTION AND IEC LOGIC SYMBOLS
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
This IC is intended for two way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The enable input G can be used to disable the
device so that the buses are effectively isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z state must
be held HIGH or LOW.
September 2001
1/10

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