Philips Semiconductors
Product specification
Single 2-input NOR gate
FEATURES
•
Wide supply voltage range from 1.65 V to 5.5 V
•
High noise immunity
•
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24
mA output drive (V
CC
= 3.0 V)
•
CMOS low power consumption
•
Latch-up performance exceeds 250 mA
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5 V
•
Multiple package options
•
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
inputs A, B to output Y
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per buffer V
CC
= 3.3 V; notes 1 and 2
DESCRIPTION
74LVC1G02
The 74LVC1G02 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Input can be driven from either 3.3 V or 5 V devices.
These features allow the use of these devices in a mixed
3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant
for slower input rise and fall time.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G02 provides the single 2-input NOR
function.
TYPICAL
3.2
2.2
2.5
2.1
1.7
5
14
UNIT
ns
ns
ns
ns
ns
pF
pF
2004 Sep 07
2
Philips Semiconductors
Product specification
Single 2-input NOR gate
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
supply voltage
input voltage
output voltage
operating ambient temperature
input rise and fall times
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
active mode
V
CC
= 0 V; Power-down mode
CONDITIONS
0
0
0
−40
0
0
MIN.
1.65
74LVC1G02
MAX.
5.5
5.5
V
CC
5.5
+125
20
10
V
V
V
V
UNIT
°C
ns/V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
PARAMETER
supply voltage
input diode current
input voltage
output diode current
output voltage
output source and sink current
V
CC
or GND current
storage temperature
power dissipation
T
amb
=
−40 °C
to +125
°C
V
I
< 0 V
note 1
V
O
> V
CC
or V
O
< 0 V
active mode; notes 1 and 2
V
O
= 0 V to V
CC
CONDITIONS
−
−0.5
−
−0.5
−
−
−65
−
MIN.
−0.5
MAX.
+6.5
−50
+6.5
±50
+6.5
±50
±100
+150
250
V
mA
V
mA
V
mA
mA
°C
mW
UNIT
V
CC
+ 0.5 V
Power-down mode; notes 1 and 2
−0.5
2004 Sep 07
5
京公网安备 11010802033920号
EEWORLD
