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5962H9654301VXA

Description
NAND Gate, ACT Series, 4-Func, 2-Input, CMOS, CDFP14, CERAMIC, DFP-14
Categorylogic    logic   
File Size226KB,9 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962H9654301VXA Overview

NAND Gate, ACT Series, 4-Func, 2-Input, CMOS, CDFP14, CERAMIC, DFP-14

5962H9654301VXA Parametric

Parameter NameAttribute value
Parts packaging codeDFP
package instructionDFP,
Contacts14
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
seriesACT
JESD-30 codeR-GDFP-F14
JESD-609 codee0
length9.525 mm
Logic integrated circuit typeNAND GATE
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)15 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose1M Rad(Si) V
width6.2865 mm
Base Number Matches1
Standard Products
UT54ACS132/UT54ACTS132
Quadruple 2-Input NAND Schmitt Triggers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS (ACTS 132) and 0.6μ CRH CMOS process
(ACS132)
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP (not available for the ACS132)
- 14-lead flatpack
UT54ACS132 - SMD 5962-96542
UT54ACTS132 - SMD 5962-96543
DESCRIPTION
The UT54ACS132 and the UT54ACTS132 are 2-input NAND
gates with Schmitt Trigger input levels. A high applied on both
the inputs forces the output to a low state.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
An
L
L
H
H
Bn
L
H
L
H
OUTPUT
Yn
H
H
H
L
PINOUTS
14-Pin DIP
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
14-Lead Flatpack
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
LOGIC DIAGRAM
A1
B1
A2
B2
Y1
Y2
LOGIC SYMBOL
A1
B1
A2
B2
A3
B3
A4
B4
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(11)
(6)
(8)
Y2
Y3
Y4
&
(3)
Y1
A3
B3
A4
B4
Y4
Y3
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984
and IEC Publication 617-12.
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