Intel
®
Ethernet Controller X550
Datasheet
Ethernet Networking Division (ND)
PRODUCT FEATURES
General
Serial Flash interface
Configurable LED operation for software or customizing OEM
LED displays
Device disable capability
Package size - 25 mm x 25 mm (X550-BT2)
Package size - 17 mm x 17 mm (X550-AT2)
Networking
10 GbE/1 GbE/100 Mb/s copper PHYs integrated on-chip
Support for jumbo frames of up to 15.5 KB
Flow control support: send/receive pause frames and receive
FIFO thresholds
Statistics for management and RMON
802.1q VLAN support
TCP segmentation offload: up to 256 KB
IPv6 support for IP/TCP and IP/UDP receive checksum
offload
Fragmented UDP checksum offload for packet reassembly
Message Signaled Interrupts (MSI)
Message Signaled Interrupts (MSI-X)
Interrupt throttling control to limit maximum interrupt rate
and improve CPU usage
Flow Director (16 x 8 and 32 x 4)
128 transmit queues
Receive packet split header
Receive header replication
Dynamic interrupt moderation
TCP timer interrupts
Relaxed ordering
Support for 64 virtual machines per port (64 VMs x 2
queues)
Support for Data Center Bridging (DCB);(802.1Qaz,
802.1Qbb, 802.1p)
Host Interface
PCIe 3.0 Base Specification
Bus width — x1, x4, x8
64-bit address support for systems using more than 4 GB of
physical memory
MAC F
UNCTIONS
Descriptor ring management hardware for transmit and
receive
ACPI register set and power down functionality supporting
D0 and D3 states
A mechanism for delaying/reducing transmit interrupts
Software-controlled global reset bit (resets everything
except the configuration registers)
Four Software-Definable Pins (SDP) per port
Wake up
IPv6 wake-up filters
Configurable flexible filter (through NVM)
LAN function disable capability
Programmable memory transmit buffers (160 KB/port)
Default configuration by NVM for all LEDs for pre-driver
functionality
Manageability
SR-IOV support
Eight VLAN L2 filters
16 Flex L3 port filters
Four Flexible TCO filters
Four L3 address filters (IPv4)
Advanced pass through-compatible management packet
transmit/receive support
SMBus interface to an external Manageability Controller (MC)
NC-SI interface to an external MC
Four L3 address filters (IPv6)
Four L2 address filters
Revision 2.2
July 2017
333369-004
Intel
®
Ethernet Controller X550 Datasheet—Revision History
Revision History
Revision
2.2
Date
July 21, 2017
Notes
Updates include the following:
• Added
Section 2.2.8.1, “Pin Differences in the X550-AT Single Port Device”.
•
Section 11.7.6.1.3
— Added reference to list of support message types.
•
Section 11.7.6.1.3
— Modified verbiage in “Value” column for Bytes 3:5 in
Table 11-44.
•
Section 12.3.9
— Added new table for X550-AT power consumption.
•
Section 12.3.10.1
— Updated values in associate table.
Updates include the following:
• Removed EEC.FLUPD bit. No longer used for triggering Shadow RAM dump.
• Removed FLUPDATE register (0x00015F54).
•
Table 3-25
— Updated description for SDP1.
•
Section 9.2.3.6.7, “Link Capabilities Register (0xAC; RO)”
— Changed default value for
ASPM support (bits 11:10) to 10b.
•
Section 11.8.3.1, “Driver Info Host Command”
— Updated
Table 11-49.
•
Table 12-3
and
Table 12-4
— Changed Device Total Power units from mW to W.
•
Table 12-20
— Updated thermal diode typical ESR value to 2.77
.
•
Table 15-2
— Updated ID Code values.
• Other miscellaneous updates.
Updates include the following:
• Updated PHY Registers section.
• Changed Max temperature in NVM mode to 102 (Tjunction max changed 107).
• Added NBASE-T information.
• Removed 10BASE-T information.
• Removed x2 lane width.
• Updated power numbers.
• Updated heat sink and other thermal information.
Initial release (Intel public)
2.1
May 10, 2016
2.0
January 8, 2016
1.9
1
October 27, 2015
1. There were no previous versions of this document released.
2
333369-004
Contents—Intel
®
Ethernet Controller X550 Datasheet
Contents
1.0
1.1
1.2
1.3
Introduction
.........................................................................................................
19
Scope .................................................................................................................................. 19
Product Overview .................................................................................................................. 19
System Configurations ..................................................................................................... 19
PCIe Interface ................................................................................................................ 21
Network Interfaces .......................................................................................................... 21
Serial Flash Interface ....................................................................................................... 21
SMBus Interface ............................................................................................................. 21
NC-SI Interface .............................................................................................................. 21
Software-Definable Pins (SDP) Interface (General-Purpose I/O)............................................. 22
LED Interface ................................................................................................................. 22
External Interfaces ................................................................................................................ 20
1.2.1
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.4
1.5
Feature Summary ................................................................................................................. 22
Overview: New Capabilities Beyond the X540 ............................................................................ 27
NBASE-T Support ............................................................................................................ 27
Filtering Capabilities ........................................................................................................ 27
IEEE 1588 Improvements................................................................................................. 27
Manageability ................................................................................................................. 28
Terminology and Acronyms .............................................................................................. 28
Byte Ordering ................................................................................................................. 28
1.5.1
1.5.2
1.5.3
1.5.4
1.6
1.6.1
1.6.2
1.7
1.8
Conventions ......................................................................................................................... 28
References ........................................................................................................................... 29
Architecture and Basic Operation ............................................................................................. 31
Transmit (Tx) Data Flow................................................................................................... 31
Receive (Rx) Data Flow .................................................................................................... 32
1.8.1
1.8.2
2.0
2.1
2.2
Pin Interface
.........................................................................................................
33
Signal Type Definition ............................................................................................................ 33
Pin Assignments ................................................................................................................... 34
PCIe .............................................................................................................................. 34
MDI............................................................................................................................... 35
Serial Flash .................................................................................................................... 36
SMBus ........................................................................................................................... 37
NC-SI ............................................................................................................................ 37
Software Defined Pins (SDPs) ........................................................................................... 38
LEDs ............................................................................................................................. 38
RSVD and No-Connect Pins............................................................................................... 39
Miscellaneous ................................................................................................................. 41
JTAG ............................................................................................................................. 42
Power Supplies ............................................................................................................... 43
External Pull-Ups............................................................................................................. 45
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
2.3
2.4
2.5
2.3.1
Pull-Up/Pull-Down Information ................................................................................................ 45
Strapping Options ................................................................................................................. 45
Ball Out — Top View Through Package ..................................................................................... 46
3.0
3.1
Interconnects
.......................................................................................................
49
PCI Express (PCIe) ................................................................................................................ 49
General Overview............................................................................................................ 49
Transaction Layer............................................................................................................ 50
3.1.1
3.1.2
333369-004
3
Intel
®
Ethernet Controller X550 Datasheet—Contents
3.1.3
3.1.4
3.1.5
3.1.6
3.2
3.3
3.2.1
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.5
3.6
3.7
3.5.1
Link Layer ...................................................................................................................... 58
Physical Layer................................................................................................................. 60
Error Events and Error Reporting....................................................................................... 64
Performance and Statistics Counters .................................................................................. 70
SMBus ........................................................................................................................... 78
Electrical Characteristics .................................................................................................. 78
NC-SI Transactions ......................................................................................................... 78
MCTP (Over PCIe or SMBus) ............................................................................................. 79
General Overview............................................................................................................ 79
Shadow RAM .................................................................................................................. 80
NVM Clients and Interfaces............................................................................................... 81
Flash Access Contention ................................................................................................... 83
Signature Field ............................................................................................................... 84
VPD Support................................................................................................................... 84
NVM Read, Write, and Erase Sequences ............................................................................. 86
Extended NVM Flows ....................................................................................................... 89
NVM Authentication Procedure .......................................................................................... 91
I
2
C Over SDP ................................................................................................................. 95
Management Interfaces ......................................................................................................... 78
Network Controller — Sideband Interface (NC-SI) ..................................................................... 78
Non-Volatile Memory (NVM) ................................................................................................... 79
Configurable I/O Pins — Software-Definable Pins (SDPs) ............................................................ 93
LEDs ................................................................................................................................... 97
Network Interface ................................................................................................................. 98
Overview ....................................................................................................................... 98
Internal MDIO Interface ................................................................................................... 99
Integrated Copper PHY Functionality ................................................................................ 100
Ethernet Flow Control (FC) ............................................................................................. 108
Inter Packet Gap (IPG) Control and Pacing........................................................................ 119
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
4.0
4.1
Initialization
.......................................................................................................
121
Power Up ........................................................................................................................... 121
Power-Up Sequence ...................................................................................................... 121
Power-Up Timing Diagram .............................................................................................. 122
Main-Power/Aux-Power Operation ................................................................................... 125
Reset Sources............................................................................................................... 126
Reset in PCI-IOV Environment ........................................................................................ 131
Reset Effects ................................................................................................................ 132
4.1.1
4.1.2
4.1.3
4.2
Reset Operation .................................................................................................................. 126
4.2.1
4.2.2
4.2.3
4.3
4.4
Queue Disable .................................................................................................................... 135
Function Disable ................................................................................................................. 136
General ....................................................................................................................... 136
Overview ..................................................................................................................... 136
Control Options............................................................................................................. 137
Event Flow for Enable/Disable Functions........................................................................... 138
Overview ..................................................................................................................... 139
BIOS Disable of the Device at Boot Time by Using the Strapping Option ............................... 140
Introduction ................................................................................................................. 140
Power-Up State ............................................................................................................ 140
4.4.1
4.4.2
4.4.3
4.4.4
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
Device Disable .................................................................................................................... 139
Software Initialization and Diagnostics ................................................................................... 140
4
333369-004
Contents—Intel
®
Ethernet Controller X550 Datasheet
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.6.8
4.6.9
4.6.10
4.6.11
4.6.12
4.6.13
4.7
Initialization Sequence ................................................................................................... 141
100 Mb/s, 1 GbE, and 10 GbE Link Initialization ................................................................ 142
Initialization of Statistics ................................................................................................ 142
Interrupt Initialization.................................................................................................... 143
Receive Initialization...................................................................................................... 143
Transmit Initialization .................................................................................................... 146
FCoE Initialization Flow .................................................................................................. 148
Virtualization Initialization Flow ....................................................................................... 148
DCB Configuration......................................................................................................... 151
Security Initialization ..................................................................................................... 161
Alternate MAC Address Support....................................................................................... 162
Access to Shared Resources ................................................................................................. 163
5.0
5.1
5.2
Power Management and Delivery
........................................................................
165
Power Targets and Power Delivery ......................................................................................... 165
Power Management ............................................................................................................. 165
Introduction to X550 Power States .................................................................................. 165
Auxiliary Power Usage ................................................................................................... 166
PCIe Link Power Management ......................................................................................... 166
Power States ................................................................................................................ 167
Timing of Power-State Transitions ................................................................................... 172
PHY Power-Down State .................................................................................................. 176
PHY Power-Down via the PHY Register ............................................................................. 177
Smart Power-Down (SPD) .............................................................................................. 177
Disable 10GBASE-T and/or 1000BASE-T Speeds ................................................................ 179
Low Power Link Up (LPLU) .............................................................................................. 179
Energy Efficient Ethernet (EEE) ....................................................................................... 184
Advanced Power Management Wake-Up ........................................................................... 187
ACPI Power Management Wake-Up .................................................................................. 187
Wake-Up Packets .......................................................................................................... 188
Wake-Up and Virtualization ............................................................................................ 192
DMA Coalescing Activation.............................................................................................. 193
DMA Coalescing Operating Mode ..................................................................................... 194
DMA Coalescing Recommended Settings........................................................................... 195
LTR Algorithm............................................................................................................... 196
LTR Initialization Flow .................................................................................................... 197
General ....................................................................................................................... 197
MC-Based Mode ............................................................................................................ 198
NVM-Based Mode .......................................................................................................... 198
Thermal Sensor Control ................................................................................................. 199
Thermal Sensor Characteristics ....................................................................................... 199
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.5
5.5.1
5.5.2
5.5.3
5.6
5.6.1
5.6.2
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
Network Interfaces Power Management .................................................................................. 176
Wake-Up ........................................................................................................................... 187
DMA Coalescing .................................................................................................................. 193
LTR ................................................................................................................................... 196
Thermal Management .......................................................................................................... 197
6.0
6.1
6.2
6.3
Non-Volatile Memory Map
...................................................................................
201
NVM Organization ............................................................................................................... 201
Protected Areas ............................................................................................................ 204
NVM Header ....................................................................................................................... 205
Software Sections ............................................................................................................... 207
6.1.1
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Analogue and Mixed Signal
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