ZL49030DDB datasheet, PDF - EEWORLD Datasheet

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ZL49030DDB: DescriptionWide Dynamic Range DTMF Receiver; CategoryWireless rf/communication Telecom circuit; File Size344KB，14 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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ZL49030DDB Overview

Wide Dynamic Range DTMF Receiver

ZL49030DDB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	SSOP, SSOP20,.3
Reach Compliance Code	compli
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	7.2 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP20,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
Maximum seat height	2 mm
Maximum slew rate	0.008 mA
Nominal supply voltage	5 V
surface mount	YES
Telecom integrated circuit types	DTMF SIGNALING CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	5.3 mm
Base Number Matches	1

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ZL49010/1, ZL49020/1, ZL49030/1

Wide Dynamic Range DTMF Receiver

Data Sheet

Features

•

Wide dynamic range (50dB) DTMF Receiver

Call progress (CP) detection via cadence

indication

4-bit synchronous serial data output

Software controlled guard time for ZL490x0

Internal guard time circuitry for ZL490x1

Powerdown option (ZL4901x & ZL4903x)

3.579MHz crystal or ceramic resonator (ZL4903x

and ZL4902x)

External clock input (ZL4901x)

Guarantees non-detection of spurious tones

Ordering Information

ZL49010DAA

ZL49011DAA

ZL49020DAA

ZL49021DAA

ZL49030DCA

ZL49030DCB

ZL49030DDA

ZL49030DDB

ZL49031DCA

ZL49031DCB

ZL49031DDA

ZL49031DDB

8 Pin PDIP

18 Pin SOIC

20 Pin SSOP

18 Pin SOIC

20 Pin SSOP

Tubes

Tape &

Tubes

Tape &

Tubes

Tape &

Tubes

Tape &

September 2003

Reel

Applications

•

Integrated telephone answering machine

End-to-end signalling

Fax Machines

-40°C to +85°C

signal and requires external software guard time to

validate the DTMF digit. The ZL490x1, with preset

internal guard times, uses a delay steering (DStD)

logic output to indicate the detection of a valid DTMF

digit. The 4-bit DTMF binary digit can be clocked out

synchronously at the serial data (SD) output. The SD

pin is multiplexed with call progress detector output. In

the presence of supervisory tones, the call progress

Description

The ZL490xx is a family of high performance DTMF

receivers which decode all 16 tone pairs into a 4-bit

binary code. These devices incorporate an AGC for

wide dynamic range and are suitable for end-to-end

signalling. The ZL490x0 provides an early steering

(ESt) logic output to indicate the detection of a DTMF

PWDN

VDD

VSS

Voltage

Bias Circuit

Steering

Circuit

High

Group

Filter

Anti-

alias

Filter

Dial

Tone

Filter

Low

Group

Filter

Digital

Detector

Algorithm

Code

Converter

and

Latch

Digital

Guard

Time

Parallel to

Serial

Converter

& Latch

ESt

DStD

ACK

AGC

Mux

OSC2

OSC1

(CLK)

Oscillator

and

Clock

Circuit

To All Chip Clocks

Energy

Detection

ZL49010/1 and ZL49030/1 only.

ZL49020/1 and ZL49030/1 only.

ZL490x1 only.

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL49010/1, ZL49020/1, ZL49030/1

Data Sheet

output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a

digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For

ZL490x0, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high,

indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt

pin to go low. For ZL490x1, an internal delayed steering counter validates the early steering signal after a

predetermined guard time which requires no external components. The delayed steering (DStD) will go high only

when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal

due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD

output will go low only after this validation period.

Energy Detection

The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists

of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal

comparator (-35dBm), the energy detector produces an energy present indication on the SD output. The integrator

ensure the SD output will remain at high even though the input signal is changing. When the input signal is

removed, the SD output will go low following the integrator decay time. Short decay time enables the signal

envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for

specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause

the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification.

As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected

at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse

applied at the ACK pin.

Serial Data (SD) Output

When a valid DTMF signal burst is present, ESt or DStD will go high. The application of four clock pulses on the

ACK pin will provide a 4-bit serial binary code representing the decoded DTMF digit on the SD pin output. The

rising edge of the first pulse applied on the ACK pin latches and shifts the least significant bit of the decoded digit

on the SD pin. The next three pulses on ACK pin will shift the remaining latched bits in a serial format (see Figure

5). If less than four pulses are applied to the ACK pin, new data cannot be latched even though ESt/DStD can be

valid. Clock pulses should be applied to clock out any remaining data bits to resume normal operation. Any

transitions in excess of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at

logic low. The 4-bit binary representing all 16 standard DTMF digits are shown in Table .

Powerdown Mode (ZL4901x/4903x)

The ZL4901x/4903x devices offer a powerdown function to preserve power consumption when the device is not in

use. A logic high can be applied at the PWDN pin to place the device in powerdown mode. The ACK pin should be

kept at logic low to avoid undefined ESt/DStD and SD outputs (see Table 3).

LOW

697

770

852

HIGH

1209

1336

1477

1209

1336

1477

1209

1336

1477

DIGIT

Table 2 - Serial Decode Bit Table

Zarlink Semiconductor Inc.

ZL49030DDB Related Products

	ZL49030DDB	ZL49030DCA	ZL49031DCA	ZL49031DDB
Description	Wide Dynamic Range DTMF Receiver	Wide Dynamic Range DTMF Receiver	Wide Dynamic Range DTMF Receiver	Wide Dynamic Range DTMF Receiver

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