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CY2410SXC-5

Description
Phase Locked Loops - PLL MediaClock Clock COM
CategoryTopical application    Wireless rf/communication   
File Size174KB,8 Pages
ManufacturerCypress Semiconductor
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CY2410SXC-5 Overview

Phase Locked Loops - PLL MediaClock Clock COM

CY2410SXC-5 Parametric

Parameter NameAttribute value
Product CategoryPhase Locked Loops - PLL
ManufacturerCypress Semiconductor
RoHSDetails
TypePLL Clock Generator
Number of Circuits1
Minimum Input Frequency13.5 MHz
Output Frequency Range27 MHz
Supply Voltage - Max3.465 V
Supply Voltage - Min3.135 V
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseSOIC-8
Height1.48 mm
Length4.98 mm
Moisture SensitiveYes
Operating Supply Voltage3.3 V
Factory Pack Quantity97
Width3.99 mm
Unit Weight0.019048 oz
CY2410
MPEG Clock Generator with VCXO
Features
Benefits
Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
VCXO with analog adjust
3.3V operation
Compatible with MK3727 (–1, –5)
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Application compatibility for a wide variety of designs
Enables design compatibility
Advanced Features
Matches nonlinear MK3727A VCXO control curve (-5)
Digital VCXO control
Electromagnetic interference (EMI) reduction for standards
compliance
Second source for existing designs
VCXO Control
Curve
Other Features
Compatible with MK3727
Matches MK3727A nonlinear
VCXO Control Curve
Part
Number
CY2410–1
CY2410–5
Outputs
1
1
Input Frequency Range
13.5-MHz pullable crystal input per
Cypress specification
13.5-MHz pullable crystal input per
Cypress specification
Output
Frequencies
1 copy of 27 MHz linear
1 copy of 27 MHz nonlinear
CY2410-1, -5 Logic Block Diagram
13.5 XIN
XOUT
OSC
Q
Φ
VCO
P
OUTPUT
DIVIDERS
27 MHz
VCXO
PLL
VDD
VSS
Cypress Semiconductor Corporation
Document #: 38-07317 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 22, 2008
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