DS1845
Dual NV Potentiometer
and Memory
www.maxim-ic.com
FEATURES
§
Two linear taper potentiometers
-
DS1845-010 one 10k, 100 position &
one 10k, 256 position
-
DS1845-050 one 10k, 100 position &
one 50k, 256 postition
-
DS1845-100 one 10k, 100 position &
one 100k, 256 position
256 bytes of EEPROM memory
Access to data and potentiometer control via
an I
2
C compatible 2-wire interface
External Write Enable pin to protect data and
potentiometer settings
Nonvolatile wiper storage
Operates from 3V or 5V supplies
Packaging: Flip Chip Package, 16-ball
CSBGA, 14-pin TSSOP
Industrial operating temperature: -40ºC to
+85ºC
SDA
SCL
A0
A1
A2
WP
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Vcc
H0
W1
H1
L1
W0
L0
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§
§
§
§
§
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14-Pin TSSOP (173 mil)
Top View
A
B
C
D
1
2
3
4
16-Ball CSBGA (4mm x 4mm)
14-Pin Flip Chip (100-mil x 100-mil) (Not
Shown)
DESCRIPTION
The DS1845 Dual NV Potentiometer and Memory consists of one 100-position linear taper
potentiometer, one 256-position linear taper potentiometer, 256 bytes of EEPROM memory, and a 2-wire
interface. The device provides an ideal method for setting bias voltages and currents in control
applications using a minimum of circuitry. The EEPROM memory allows a user to store configuration
or calibration data for a specific system or device as well as provide control of the potentiometer wiper
settings. Any type of user information may reside in the first 248 bytes of this memory. The next two
addresses of EEPROM memory are for potentiometer settings. Access to this EEPROM is via an
industry standard 2-wire bus. The wiper position of the DS1845, as well as EEPROM data, can be
hardware write-protected using the Write Protect (WP) input pin. Up to eight DS1845s can be installed
on a single 2-wire bus. Access to an individual device is achieved by using a device address that is
determined by the logic levels of address pins A0 though A2. Additionally, the DS1845 will operate
from 3 volt or 5 volt supplies. Three package options are available: Flip Chip Package, 16-ball CSBGA
and 14-pin TSSOP.
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011006
DS1845
PIN DESCRIPTIONS
Name TSSOP BGA
V
CC
14
A3
GND
SDA
SCL
WP
7
1
2
6
D1
B2
A2
C1
Description
Power Supply Terminal.
The DS1845 will support supply
voltages ranging from +2.7V to +5.5V.
Ground Terminal.
2-Wire serial data interface.
The serial data pin is for serial data
transfer to and from the DS1845. The pin is open drain and may
be wire-ORed with other open drain or open collector interfaces.
2-Wire Serial Clock Input.
The serial clock input is used to
clock data into the DS1845 on rising edges and clock data out on
falling edges.
Write Protect Input.
If set to logic 0, the data in memory and the
potentiometer wiper setting may be changed. If set to logic 1, both
the memory and the potentiometer wiper settings will be write
protected. The WP pin is pulled high internally.
Address Input.
Pins A0, A1, and A2 are used to specify the
address of each DS1845 when used in a multi-dropped
configuration. Up to eight DS1845s may be addressed on a single
2-wire bus.
Address Input.
Address Input.
High terminal of Potentiometer 0.
For both potentiometers, it is
not required that the high terminal be connected to a potential
greater than the low terminal. Voltage applied to the high terminal
of each potentiometer cannot exceed V
CC
or go below ground.
High terminal of Potentiometer 1.
Low terminal of Potentiometer 0.
For both potentiometers, it is
not required that the low terminal be connected to a potential less
than the high terminal. Voltage applied to the low terminal of each
potentiometer cannot exceed V
CC
or go below ground.
Low terminal of Potentiometer 1.
Wiper terminal of Pot 0.
The wiper position of Potentiometer 0
is determined by the byte at EEPROM memory location F9h.
Voltage applied to the wiper terminal of each potentiometer cannot
exceed the power supply voltage, V
CC
, or go below ground.
Wiper terminal of Pot 1.
The wiper position of Potentiometer 1
is determined by the byte at EEPROM memory location F8h.
No Connect.
No Connect.
A0
3
A1
A1
A2
H0
4
5
13
B1
C2
A4
H1
L0
11
8
B3
D3
L1
W0
10
9
C4
D4
W1
NC
NC
12
B4
C3
D2
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DS1845
DS1845 BLOCK DIAGRAM
Figure 1
248 BYTES
EEPROM
MEMORY
CONTROL 6 RESERVED
BYTES
POTENTIOMETER 0
H0
100
Position
Pot
W0
L0
VCC
GND
SDA
SCL
WP
2-WIRE
INTERFACE
DATA
A0
A1
A2
1 BYTE WIPER
SETTING
POT 0
POTENTIOMETER 1
1 BYTE WIPER
SETTING
POT 1
256
Position
Pot
H1
W1
L1
MEMORY ORGANIZATION
The DS1845’s serial EEPROM is internally organized with 256 words of 1 byte each. Each word requires
an 8-bit address for random word addressing. The byte at address F9h determines the wiper setting for
potentiometer 0, which contains 100 positions. Writing values above 63h to this address sets the wiper to
its uppermost position. The byte at address F8h determines the wiper setting for potentiometer 1, which
contains 256 positions (00h to FFh). The factory default wiper position for both potentiometers is FFh.
Memory locations 00h to F7h are factory programmed to 00h. Address locations FAh though FFh are
reserved and should not be written.
DEVICE OPERATION
Clock and Data Transitions:
The SDA pin is normally pulled high with an external resistor or device.
Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high
periods will indicate a start or stop conditions depending on the conditions discussed below. Refer to the
timing diagram Fig 2 for further details.
Start Condition:
A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command. Refer to the timing diagram Fig 2 for further details.
Stop Condition:
A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command places the DS1845 into a low-power mode. Refer to the timing diagram Fig
2 for further details.
Acknowledge:
All address and data byte are transmitted via a serial protocol. The DS1845 pulls the
SDA line low during the ninth clock pulse to acknowledge that it has received each word.
Standby Mode:
The DS1845 features a low-power mode that is automatically enabled after power-on,
after a stop command, and after the completion of all internal operations.
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DS1845
2-Wire Interface Reset:
After any interruption in protocol, power loss, or system reset, the following
steps reset the DS1845.
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition while SDA is high.
Device Addressing:
The DS1845 must receive an 8-bit device address word following a start condition
to enable a specific device for a read or write operation. The address word is clocked into the DS1845
MSB to LSB. The address word consists of Ah (1010) followed by A2, A1, and A0 then the R/W
(READ/WRITE) bit. If the R/W bit is high, a read operation is initiated. The R/W is low, a write
operation is initiated. For a device to become active, the values of A2, A1 and A0 must be the same as
the hard-wired address pins on the DS1845. Upon a match of written and hard-wired addresses, the
DS1845 will output a zero for one clock cycle as an acknowledge. If the address does not match the
DS1845 returns to a low-power mode.
Write Operations:
After receiving a matching address byte with the R/W bit set low, the device goes
into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to the
device to define the address where the data is to be written. After the reception of this byte, the DS1845
will transmit a zero for one clock cycle to acknowledge the receipt of the address. The master must then
transmit an 8-bit data word to be written into this address. The DS1845 will again transmit a zero for one
clock cycle to acknowledge the receipt of the data. At this point the master must terminate the write
operation with a stop condition. The DS1845 then enters an internally timed write process t
w
to the
EEPROM memory. All inputs are disabled during this byte write cycle.
The DS1845 is capable of an 8-byte page write. A page write is initiated the same way as a byte write,
but the master does not send a stop condition after the 1
st
byte. Instead, after the slave acknowledges
receipt of the data byte, the master can send up to seven more bytes using the same nine-clock sequence.
The master must terminate the write cycle with a stop condition or the data clocked into the DS1845 will
not be latched into permanent memory.
Acknowledge Polling:
Once the internally-timed write has started and the DS1845 inputs are disabled,
acknowledge polling can be initiated. The process involves transmitting a start condition followed by the
device address. The R/W bit signifies the type of operation that is desired. The read or write sequence
will only be allowed to proceed if the internal write cycle has completed and the DS1845 responds with a
zero.
Read Operations:
After receiving a matching address byte with the R/W bit set high, the device goes
into the read mode of operation. There are three read operations: current address read, random read and
sequential address read.
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DS1845
CURRENT ADDRESS READ
The DS1845 has an internal address register that maintains the address used during the last read or write
operation, incremented by one. This data is maintained as long as V
CC
is valid. If the most recent
address was the last byte in memory, then the register resets to the first address. This address stays valid
between operations as long as power is available.
Once the device address is clocked in and acknowledged by the DS1845 with the R/W bit set to high, the
current address data word is clocked out. The master does not respond with a zero, but does generate a
stop condition afterwards.
RANDOM READ
A random read requires a dummy byte write sequence to load in the data word address. Once the device
and data address bytes are clocked in by the master, and acknowledged by the DS1845, the master must
generate another start condition. The master now initiates a current address read by sending the device
address with the read/write bit set high. The DS1845 will acknowledge the device address and serially
clocks out the data byte.
SEQUENTIAL ADDRESS READ
Sequential reads are initiated by either a current address read or a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1845 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1845.
After reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the master initiates a stop condition. The master does
not respond with a zero.
For a more detailed description of 2-wire theory of operation, refer to the following section.
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. The DS1845 operates as
a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2. Timing diagrams for
the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is
provided in the AC Electrical Characteristics table for 2-wire serial communications.
The following bus protocol has been defined:
-
-
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy:
Both data and clock lines remain HIGH.
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