2.5V LVDS 1:16 Clock Fanout Buffer
8T349316
DATASHEET
General Description
The 8T349316 is a 2.5V differential clock buffer with sixteen LVDS
outputs. The fanout from a differential input to the sixteen LVDS
outputs reduces loading on the preceding driver and provides an
efficient clock distribution network. The 8T349316 can act as a
translator from a differential HSTL, LVPECL, CML or LVDS input to
LVDS output signals. A single-ended 3.3V, 2.5V LVCMOS/LVTTL
input can also be used to translate to LVDS outputs. The redundant
input capability allows for an asynchronous change-over from a
primary clock source to a secondary clock source. Selectable
reference inputs are controlled by SEL. The 8T349316 outputs can
be asynchronously enabled/disabled. When disabled, the outputs
will drive to the value selected by the GL pin. Multiple power and
grounds reduce noise.The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Clock signal selection and fanout to 16 LVDS outputs
Guaranteed Low Skew < 50ps (max)
Low output pulse skew < 125ps (max)
Propagation delay < 1.75ns (max)
Up to 1GHz clock signal operation
Support the following input types: HSTL, LVPECL, HCSL, LVTTL
Selectable differential input
Power-down mode
Full 2.5V power supply
-40°C to +85°C ambient operating temperature
Lead-free (RoHS 6) 52-lead VFQFN-P packaging
Replacement device for the 5T9316
Block Diagram
A1
nA1
A2
nA2
SEL
GL
1
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
Pin Assignment
nQ16
nQ15
nQ14
nQ13
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Q12
nQ12
Q13
nQ14
Q15
nQ15
Q16
nQ16
nPD
SEL
Q16
Q15
Q14
Q13
V
DD
V
DD
0
52 51 50 49 48 47 46 45 44 43 42 41 40
nG1
V
DD
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
V
DD
A1
nA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 17 19 20 21 22 23 24 25 26
nc
39
38
37
36
35
34
nG2
V
DD
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
V
DD
A2
nA2
8T349316
33
32
31
30
29
28
27
nG1
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
nG2
GND
V
DD
nQ5
nQ6
nQ7
nPD
POWER DOWN
CTRL
OUT
CTRL
OUT
CTRL
52-lead VFQFN-P, EPad
8mm x 8mm x 0.9mm Package body
NL package
Top View
8T349316 REVISION 2 11/2/14
1
©2014 Integrated Device Technology, Inc.
nQ8
V
DD
GL
Q5
Q6
Q7
Q8
nc
8T349316 DATASHEET
Pin Description and Pin Characteristic Tables
Table 1: Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
nG1
V
DD
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
V
DD
A1
nA1
GL
V
DD
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
DD
GND
nc
nA2
A2
V
DD
nQ9
Q9
nQ10
Q10
nQ11
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Input
Input
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
-
Input
Input
Power
Output
Output
Output
Output
Output
-
-
-
-
-
-
Type
-
Description
Output enable control input for the Q[1:8] differential outputs.
See
Table 3C.
LVCMOS/LVTTL interface levels.
Positive power supply voltage.
Differential clock output Q1. LVDS interface signals.
Differential clock output Q1. LVDS interface signals.
Differential clock output Q2. LVDS interface signals.
Differential clock output Q2. LVDS interface signals.
Differential clock output Q3. LVDS interface signals.
Differential clock output Q3. LVDS interface signals.
Differential clock output Q4. LVDS interface signals.
Differential clock output Q4. LVDS interface signals.
Positive power supply voltage.
Differential clock signal input 1.
Differential clock signal input 1.
Control input for the output level for outputs in disable state.
See
Table 3C
and
Table 3D.
LVCMOS/LVTTL interface levels.
Positive power supply voltage.
Differential clock output Q5. LVDS interface signals.
Differential clock output Q5. LVDS interface signals.
Differential clock output Q6. LVDS interface signals.
Differential clock output Q6. LVDS interface signals.
Differential clock output Q7. LVDS interface signals.
Differential clock output Q7. LVDS interface signals.
Differential clock output Q8. LVDS interface signals.
Differential clock output Q8. LVDS interface signals.
Positive power supply voltage.
Power Supply Ground.
Not connected. It is recommended to connect this pin to board GND (0V).
Differential clock signal input 2.
Differential clock signal input 2.
Positive power supply voltage.
Differential clock output Q9. LVDS interface signals.
Differential clock output Q9. LVDS interface signals.
Differential clock output Q10. LVDS interface signals.
Differential clock output Q10. LVDS interface signals.
Differential clock output Q11. LVDS interface signals.
2.5V LVDS 1:16 CLOCK FANOUT BUFFER
2
REVISION 2 11/2/14
8T349316 DATASHEET
Table 1: Pin Descriptions
Number
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
—
Name
Q11
nQ12
Q12
V
DD
nG2
nc
nPD
V
DD
nQ13
Q13
nQ14
Q14
nQ15
Q15
nQ16
Q16
V
DD
SEL
GND
Output
Output
Output
Power
Input
-
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Input
Power
-
-
-
Type
Description
Differential clock output Q11. LVDS interface signals.
Differential clock output Q12. LVDS interface signals.
Differential clock output Q12. LVDS interface signals.
Positive power supply voltage.
Output enable control input for the Q[9:16] differential outputs.
See
Table 3D.
LVCMOS/LVTTL interface levels.
Not connected. It is recommended to connect this pin to board GND (0V).
Device power-down control input.
See
Table 3B.
LVCMOS/LVTTL interface levels.
Positive power supply voltage.
Differential clock output Q13. LVDS interface signals.
Differential clock output Q13. LVDS interface signals.
Differential clock output Q14. LVDS interface signals.
Differential clock output Q14. LVDS interface signals.
Differential clock output Q15. LVDS interface signals.
Differential clock output Q15. LVDS interface signals.
Differential clock output Q16. LVDS interface signals.
Differential clock output Q16. LVDS interface signals.
Positive power supply voltage.
Reference input signal select control pin.
See
Table 3A.
LVCMOS/LVTTL interface levels.
Exposed package ground supply voltage (GND). Connect to board GND.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
GL, nG1, nG2, nPD, SEL
Minimum
Typical
Maximum
3
Units
pF
REVISION 2 11/2/14
3
2.5V LVDS 1:16 CLOCK FANOUT BUFFER
8T349316 DATASHEET
Logic Truth Tables
Table 3A: Input Signal Source Select
1
SEL
0
1
Input Selection
A2
A1
1. Asynchronous control.
Table 3B. Device Power-down control
1
nPD
0
1
Power-down Operation
Power-down mode of the entire device. Input and outputs disable and the output
voltage is V
DD
(for each Q1, nQ1 to Q16, nQ16 pair)
2
Normal 0peration
1. Asynchronous control.
2. Disable outputs by setting nG1 = nG2 = 1 before entering power-down mode and while in
power-down mode. To enter normal device operation, first enable the outputs by setting
nG1 = nG2 = 0 before setting nPD = 1.
Table 3C. Output Q[1:8] Enable Control
1
GL
X
0
1
nG1
0
1
1
Q1 to Q8 Output State
Enabled (active)
Disabled, output state is logic low (Q[1:8] = L, nQ[1:8] = H)
Disabled, output state is logic high (Q[1:8] = H, nQ[1:8] = L)
1. Asynchronous controls.
Table 3D. Output Q[9:16] Enable Control
1
GL
X
0
1
nG2
0
1
1
Q9 to Q16 Output State
Enabled (active)
Disabled, output state is logic low (Q[9:16] = L, nQ[9:16] = H)
Disabled, output state is logic high (Q[9:16] = H, nQ[9:16] = L)
1. Asynchronous controls.
2.5V LVDS 1:16 CLOCK FANOUT BUFFER
4
REVISION 2 11/2/14
8T349316 DATASHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 4. Absolute Maximum Ratings
Item
Supply Voltage, V
DD
Input Voltage
Output Voltage
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Storage Temperature
Thermal Junction Temperature, T
J
Rating
-0.5V to 3.6V
-0.5V to 3.6V
-0.5V to V
DD
+ 0.5V and <3.6V
10mA
15mA
-65°C to 150°C
125C
Table 5. Recommended Operating Range
Item
Supply Voltage, V
DD
Ambient Temperature
Minimum
2.3
-40
Typical
2.5
Maximum
2.7
+85
Units
V
°C
REVISION 2 11/2/14
5
2.5V LVDS 1:16 CLOCK FANOUT BUFFER
Embedded System
京公网安备 11010802033920号
EEWORLD
