Datasheet
Serial EEPROM Series Standard EEPROM
WLCSP EEPROM
BU9889GUL-W
(8Kbit)
●Package
W(Typ.) x D(Typ.) x H(Max.)
VCSP50L1 1.60mm x 1.00mm x 0.55mm
●General
Description
BU9889GUL-W is a serial EEPROM of I
2
C BUS interface method.
●Features
■
Completely conforming to the world standard I
2
C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data
(SDA)
■
1k words×8 bits architecture 8kbit serial EEPROM.
■
Other devices than EEPROM can be connected to the same port,
saving microcontroller port.
■
1.7V to 5.5V single power source action most suitable for battery use.
■
FAST MODE 400kHz at 1.7V to 5.5V
■
Page write mode useful for initial value write at factory shipment.
■
Auto erase and auto end function at data rewrite.
■
Low current consumption
At write operation (5V)
: 0.5mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1µA (Typ.)
■
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
■
Data rewrite up to 100,000 times
■
Data kept for 40 years
■
Noise filter built in SCL / SDA terminal
■
Shipment data all address FFh
●Absolute
Maximum Ratings
(Ta=25℃)
Parameter
symbol
Impressed voltage
Permissible dissipation
Storage temperature range
Action temperature range
Terminal voltage
V
CC
Pd
Tstg
Topr
-
Limits
-0.3 to +6.5
220
-65 to +125
-40 to +85
-0.3 to V
CC
+1.0
Unit
V
mW
℃
℃
V
Remarks
When using at Ta=25℃ or higher, 2.2mW to be reduced per 1℃
●Memory
cell characteristics
(Ta=25℃, Vcc=1.7V to 5.5V)
Limits
Parameter
Min.
Typ.
Number of data rewrite times *1
Data hold years *1
Shipment data all address FFh
*1 Not 100% TESTED
Max.
-
-
Unit
Times
Years
100,000
40
-
-
●Recommended
Operating Ratings
Parameter
Power source voltage
Input voltage
Symbol
V
CC
V
IN
Limits
1.7 to 5.5
0 to V
CC
Unit
V
○Product
structure：Silicon monolithic integrated circuit
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This
product is not designed protection against radioactive rays
1/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
BU9889GUL-W (8Kbit)
●Electrical
Characteristics
Parameter
"H" Input Voltage1
"L" Input Voltage1
"L" Output Voltage1
"L" Output Voltage2
Input Leakage Current
Output Leakage Current
(Unless otherwise specified Ta=-40℃ to +85℃, Vcc=1.7V to 5.5V)
Limits
Symbol
Unit
Min
Typ.
Max.
V
IH1
V
IL1
V
OL1
V
OL2
I
LI
I
LO
I
CC1
Current consumption at action
I
CC2
Standby Current
●Action
timing characteristics
I
SB
-
-
-
-
0.5
2.0
mA
μA
0.7V
CC
-0.3
-
-
-1
-1
-
-
-
-
-
-
-
-
V
CC
+1.0
0.3V
CC
0.4
0.2
1
1
2.0
V
V
V
V
μA
μA
mA
Datasheet
Condition
I
OL
=3.0mA , 2.5V≦V
CC
≦5.5V
(SDA)
I
OL
=0.7mA , 1.7V≦V
CC
≦2.5V
(SDA)
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
(SDA)
V
CC
=5.5V, fSCL =400kHz, tWR=5ms
Byte Write, Page Write
V
CC
=5.5V, fSCL =400kHz
Random read, Current read, Sequential read
V
CC
=5.5V, SDA・SCL=V
CC
A2=GND, WP=GND
(Unless otherwise specified Ta=-40℃ to +85℃, Vcc=1.7V to 5.5V)
Limits
Parameter
Symbol
Min.
Typ.
fSCL
tHIGH
tLOW
*1
*1
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
-
0.6
1.2
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
-
0
0.1
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
400
-
-
0.3
0.3
-
-
-
-
0.9
-
-
-
5
0.1
-
-
-
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
SCL Frequency
Data clock "High" time
Data clock "Low" time
SDA, SCL rise time
SDA, SCL fall time
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition data setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA,SCL terminal)
WP hold time
WP setup time
WP valid time
*1 : Not 100% TESTED
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
2/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
BU9889GUL-W (8Kbit)
●Sync
Data Input / Output Timing
tR
SCL
tHD:STA
(Input)
(入力)
Datasheet
tF
tHIGH
SCL
tSU:DAT
tLOW
tHD:DAT
SDA
DATA(1)
D1
D0
ACK
DATA(n)
ACK
½WR
SDA
tBUF
SDA
(Output)
(出力)
tPD
tDH
WP
Stop condition
ストップコンディション
tSU：WP
½HD：WP
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
Figure 1-(d) WP timing at write execution
SCL
tSU:STA
SDA
SCL
tHD:STA
tSU:STO
DATA(1)
SDA
D1
D0
ACK
DATA(n)
ACK
tHIGH:WP
tWR
START BIT
STOP BIT
WP
○
At write execution, in the area from the D0 taken clock rise of the first DATA(1),
to tWR, set WP= 'LOW'.
○
By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under
access is not guaranteed, therefore write it once again.
Figure 1-(b) Start - stop bit timing
Figure 1-(e) WP timing at write cancel
SCL
SDA
D0
ACK
WRITE DATA(n)
STOP
CONDITION
t
WR
START
CONDITION
Figure 1-(c) Write cycle timing
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
3/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
BU9889GUL-W (8Kbit)
●Block
Diagram
Datasheet
Vcc
8K½½½ ＥＥＰＲＯＭ ARRAY
GND
10bit
ADDRESS
DECODER
SLAVE、WORD
8bit
DATA
REGISTER
10bit
ADDRESS REGISTER
WP
START
STOP
A2
CONTROL LOGIC
ACK
SCL
HIGH VOLTAGE GEN.
Vcc LEVEL DETECT
SDA
●Pin
Configuration
(BOTTOM VIEW)
B
A
○ ○ ○
○ ○ ○
B1
B2
B3
SDA
A1
GND
A2
A2
A3
SCL
WP
V
CC
1
●Pin
Descriptions
Terminal name
A2
GND
SDA
SCL
WP
Vcc
Input/ Output
Input
-
Input / Output
Input
Input
-
2
3
Function
Slave address setting
Reference voltage of all input / output, 0V.
Slave and word address,
Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
4/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
BU9889GUL-W (8Kbit)
●Typical
Performance Curves
(The following values are Typ. ones.)
Datasheet
Figure 2. ‘H’ input voltage V
IH
(A2, SCL, SDA, WP)
Figure 3. ‘L’ input voltage V
IL
(A2, SCL, SDA, WP)
Figure 4. ‘L’ output voltage V
OL
-I
OL
(Vcc=1.7V)
Figure 5. ‘L’ output voltage V
OL
-I
OL
(Vcc=2.5V)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
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