The DS1220Y 16k Nonvolatile SRAM is a 16,384-bit, fully static, nonvolatile RAM organized as 2048
words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that
constantly monitor V
CC
for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAM can be used in place of existing 2k x 8 SRAMs directly conforming to
the popular bytewide 24-pin DIP standard. The DS1220Y also matches the pinout of the 2716 EPROM or
the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
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NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
READ MODE
The DS1220Y executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 11 address inputs
(A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
CE
and
OE
access times are also satisfied. If
CE
and OE access times are not satisfied, then data
access must be measured from the later-occurring signal and the limiting parameter is either t
CO
for
CE
or
t
OE
for
OE
rather than address access.
WRITE MODE
The DS1220Y executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of
CE
or
WE
will determine the start of the write
cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be
kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time
(t
WR
) before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active)
then WE will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1220Y provides full-functional capability for V
CC
greater than 4.5 volts and write protects at 4.25
nominal. Data is maintained in the absence of V
CC
without any additional support circuitry. The
DS1220Y constantly monitors V
CC
. Should the supply voltage decay, the NV SRAM automatically write
protects itself, all inputs become “don’t care,” and all outputs become high-impedance. As V
CC
falls
below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when V
CC
rises above approximately 3.0 volts, the power switching circuit
connects external V
CC
to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after V
CC
exceeds 4.5 volts.
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NOT RECOMMENDED FOR NEW DESIGNS
DS1220Y
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
Industrial:
Storage Temperature
Lead Temperature (soldering, 10s)
Note:
EDIP is wave or hand soldered only.
-0.3V to +6.0V
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
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