PHP18NQ10T
N-channel TrenchMOS standard level FET
Rev. 02 — 16 December 2010
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Higher operating power due to low
thermal resistance
Low conduction losses due to low
on-state resistance
Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
DC-to-DC converters
Switched-mode power supplies
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
gate-drain charge
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
mb
= 25 °C; V
GS
= 10 V
T
mb
= 25 °C
V
GS
= 10 V; I
D
= 9 A;
T
j
= 25 °C
V
GS
= 10 V; I
D
= 18 A;
V
DS
= 80 V; T
j
= 25 °C
Min
-
-
-
-
Typ
-
-
-
80
Max Unit
100
18
79
90
V
A
W
mΩ
Static characteristics
Dynamic characteristics
Q
GD
-
8
-
nC
NXP Semiconductors
PHP18NQ10T
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3
SOT78 (TO-220AB)
3. Ordering information
Table 3.
Ordering information
Package
Name
PHP18NQ10T
TO-220AB
Description
plastic single-ended package; heatsink mounted; 1 mounting
hole; 3-lead TO-220AB
Version
SOT78
Type number
PHP18NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 16 December 2010
2 of 13
NXP Semiconductors
PHP18NQ10T
N-channel TrenchMOS standard level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
non-repetitive avalanche current
T
mb
= 25 °C
pulsed; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 11 A;
V
sup
≤
25 V; unclamped; t
p
= 100 µs;
R
GS
= 50
Ω
V
sup
≤
25 V; V
GS
= 10 V; T
j(init)
= 25 °C;
R
GS
= 50
Ω;
unclamped
V
GS
= 10 V; T
mb
= 100 °C
V
GS
= 10 V; T
mb
= 25 °C
pulsed; T
mb
= 25 °C
T
mb
= 25 °C
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
100
100
20
13
18
72
79
175
175
18
72
70
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
I
AS
-
18
A
100
P
D
(%)
80
003aae629
100
I
D
(%)
80
003aae630
60
60
40
40
20
20
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig 2.
Normalized continuous drain current as a
function of mounting base temperature
PHP18NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 16 December 2010
3 of 13
NXP Semiconductors
PHP18NQ10T
N-channel TrenchMOS standard level FET
10
2
I
DM
(A)
10
003aae631
R
DS(on)
= V
DS
/ I
D
t
p
= 10
μs
100
μs
D.C.
1 ms
10 ms
100 ms
10
2
I
AS
(A)
10
25
°C
003aae643
1
1
T
j
prior to avalanche = 150
°C
10
−1
1
10
10
2
V
DS
(V)
10
3
10
−1
10
−3
10
−2
10
−1
1
t
AV
(ms)
10
T
mb
= 25 °C; I
DM
is single pulse
Fig 3.
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
Fig 4.
unclamped inductive load
Single-shot avalanche rating; avalanche
current as a function of avalanche period
PHP18NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 16 December 2010
4 of 13
NXP Semiconductors
PHP18NQ10T
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction to mounting
base
thermal resistance from junction to ambient
in free air
Conditions
Min
-
-
Typ
-
60
Max
1.9
-
Unit
K/W
K/W
10
Z
th(j-mb)
(K/W)
1
D = 0.5
0.2
0.1
10
−1
0.05
0.02
single pulse
10
−2
10
−6
10
−5
10
−4
10
−3
t
p
T
P
003aae632
δ
=
t
p
T
t
10
−2
10
−1
1
t
p
(s)
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHP18NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 16 December 2010
5 of 13
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