CY28RS480-1
Clock Generator for ATI
®
RS480 Chipset
Features
• Supports AMD CPU
• Selectable CPU frequencies
• 200 MHz differential CPU clock pairs
• 100 MHz differential SRC clocks
• 48 MHz USB clock
• 33 MHz PCI clock
CPU
x2
SRC
x8
HTT66
x1
PCI
x1
REF
x3
USB_48
x1
• 66 MHz HyperTransport clock
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
Block Diagram
XIN
XOUT
CPU_STP#
CLKREQ[0:1]#
Pin Configuration
VDD_REF
REF[0:2]
XTAL
OSC
PLL1
PLL Ref Freq
Divider
Network
VDD_CPU
CPUT[0:2], CPUC[0:2],
VDD_SRC
SRCT[0:6],SRCC[0:6]
VDD_SRCS
SRCST[0:1],SRCSC[0:1]
VDD_PCI
PCI
VDD_HTT
HTT66
IREF
PD
VDD_48 MHz
PLL2
USB_48
SDATA
SCLK
I
2
C
Logic
XIN
XOUT
VDD_48
USB_48
VSS_48
CLK_STOP
SCLK
SDATA
NC
CLKREQ#0
CLKREQ#1
SRCT5
SRCC5
VDD_SRC
VSS_SRC
SRCT4
SRCC4
SRCT3
SRCC3
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
SRCST1
SRCSC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_REF
VSS_REF
REF0
REF1
REF2
VDD_PCI
PCI0
VSS_PCI
VDD_HTT
HTT66
VSS_HTT
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
VDDA
VSSA
IREF
VSS_SRC
VDD_SRC
SRCT0
SRCC0
VDD_SRC1
VSS_SRC1
SRCST0
SRCSC0
56 SSOP/TSSOP
CY28RS480-1
....................... Document #: 38-07714 Rev. *C Page 1 of 16
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
CY28RS480-
Pin Description
Pin No.
41,40,45,44
50
37
52, 53, 54
7
8
27, 28, 30, 29
12, 13, 16,
17, 18, 19,
22, 23, 24,
25, 34, 33
10,11
Name
CPUT/C
PCI0
IREF
REF[2:0]
SCLK
SDATA
SRCST/C[1:0]
SRCT/C[5:0]
Type
O
I
33-MHz clock output.
A precision resistor attached to this pin is connected to the internal current
reference.
SMBus-compatible SCLOCK.This
pin has an internal pull-up, but is tri-stated in
power-down.
Description
O, DIF
Differential CPU clock outputs.
AMD
K8 buffer (200 MHz).
O, SE
14.318-MHz REF clock output.
Intel
Type-5 buffer.
I,PU
I/O,PU
SMBus-compatible SDATA.This
pin has an internal pull-up, but is tri-stated in
power-down.
O, DIF
Differentials Selectable serial reference clock.
Intel Type-X buffer.
Includes overclock support through SMBUS
O, DIF
100-MHz differential serial reference clock.
Intel Type-X buffer.
CLKREQ#[0:1]
I, SE,
Output Enable control for SRCT/C.
Output enable control required by Minicard
PD specification. This pin has an internal pull down. 0 = selected SRC output is
enabled.1 = selected SRC output is disabled.
O, SE
48-MHz clock output.
Intel Type-3A buffer.
O, SE
66-MHz clock output.
Intel Type-5 buffer.
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
GND
GND
I
O
I,PU
3.3V power supply for USB outputs
3.3V power supply for CPU outputs
3.3V power supply for PCI outputs
3.3V power supply for REF outputs
3.3V power supply for Hyper Transport outputs
3.3V power supply for SRC outputs
3.3V power supply for SRCS outputs
3.3V Analog Power for PLLs
Ground for USB outputs
Ground for CPU outputs
Ground for PCI outputs
Ground for REF outputs
Ground for SRC outputs
Ground for SRCS outputs
Ground for HyperTransport outputs
Analog Ground
14.318-MHz Crystal Input
14.318-MHz Crystal Output
3.3V LVTTL Input
When this pin is asserted HIGH, all clock outputs except for CPUCLKs (pins 41,
40, 45, 44) are halted at logic level 0. This pin has internal pull-up
No Connects
4
47
3
43
51
56
48
14, 21, 35
32
39
5
42
49
55
15, 20, 26, 36
31
46
38
1
2
6
USB_48
HTT66
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_HTT
VDD_SRC
VDD_SRCS
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSS_SRCS
VSS_HTT
VSSA
XIN
XOUT
CLK_STOP
9
NC
.......................Document #: 38-07714 Rev. *C Page 2 of 16
CY28RS480-
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
7
(6:5)
(4:0)
Chip select address, set to ‘00’ to access device
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
Start
Slave address – 7 bits
Write
Acknowledge from slave
Description
Bit
1
8:2
9
10
Start
Slave address – 7 bits
Write
Acknowledge from slave
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Block Read Protocol
Description
.......................Document #: 38-07714 Rev. *C Page 3 of 16
CY28RS480-
Table 3. Byte Read and Byte Write Protocol
(continued)
Byte Write Protocol
Bit
18:11
19
27:20
28
29
Description
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Bit
18:11
19
20
27:21
28
29
37:30
38
39
Byte Read Protocol
Description
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Control Registers
Byte 0:Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC [T/C]0
SRCS[T/C]1
SRCS[T/C]0
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Description
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
REF2
REF1
REF0
PCI0
USB_48
RESERVED
CPU[T/C]1
CPU[T/C]0
REF2 Output Enable
0 = Disable, 1 = Enable
REF1 Output Enable
0 = Disable, 1 = Enable
REF0 Output Enable
0 = Disable, 1 = Enable
PCI0 Output Enable
0 = Disable, 1 = Enable
USB_48MHz Output Enable
0 = Disable, 1 = Enable
RESERVED
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Description
.......................Document #: 38-07714 Rev. *C Page 4 of 16
CY28RS480-
Byte 2: Control Register 2
Bit
7
@Pup
1
Name
CPUT/C
SRCT/C
USB_48
PCI
Reserved
Reserved
CPU
SRC
Reserved
Reserved
Spread Spectrum Selection
‘0’ = -0.35%
‘1’ = -0.50%
48-MHz Output Drive Strength
0 = 1x, 1 = 2x
33-MHz Output Drive Strength
0 = 1x, 1 = 2x
Reserved
Reserved
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Reserved
Reserved
Description
6
5
4
3
2
1
0
1
1
0
1
0
1
1
Byte 3: Control Register 3
Bit
7
@Pup
1
Name
CLKREQ#
Description
CLKREQ# drive mode
0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when
stopped
Reserved, Set = 0
Reserved, Set = 1
Reserved, Set = 0
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
HTT66 Output Drive Strength 0 = High drive, 1 = Low drive.
6
5
4
3
2
1
0
0
1
0
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HTT66
Byte 4: Control Register 4
Bit
7
@Pup
0
Name
SRC[T/C]5
Description
SRC[T/C]5 CLKREQ0 control
1 = SRC[T/C]5 stoppable by CLKREQ#0 pin
0 = SRC[T/C]5 free running
SRC[T/C]4 CLKREQ#0 control
1 = SRC[T/C]4 stoppable by CLKREQ#0 pin
0 = SRC[T/C]4 free running
SRC[T/C]3 CLKREQ#0 control
1 = SRC[T/C]3 stoppable by CLKREQ#0 pin
0 = SRC[T/C]3 free running
SRC[T/C]2 CLKREQ#0 control
1 = SRC[T/C]2 stoppable by CLKREQ#0 pin
0 = SRC[T/C]2 free running
SRC[T/C]1 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
SRC[T/C]0 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
HTT66 Output enable
0 = disabled, 1 = enabled
Reserved
6
0
SRC[T/C]4
5
0
SRC[T/C]3
4
0
SRC[T/C]2
3
0
SRC[T/C]1
2
0
SRC[T/C]0
1
0
1
1
HTT66
Reserved
.......................Document #: 38-07714 Rev. *C Page 5 of 16
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