3.3 V/2.5 V 1:15 PECL/LVCMOS Clock
Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted
for high performance clock tree applications. With output frequencies up to
200 MHz and output skews less than 200 ps the device meets the needs of the
most demanding clock applications.
Features
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15 LVCMOS compatible clock outputs
Two selectable LVCMOS and one differential LVPECL compatible clock
inputs
Selectable output frequency divider (divide-by-one and divide-by-two)
Maximum clock frequency of 200 MHz
Maximum clock skew of 200 ps
High-impedance output control
3.3 V or 2.5 V power supply
Drives up to 30 series terminated clock lines
Ambient temperature range –40C to +85C
52-lead LQFP packaging, Pb-free
Supports clock distribution in networking, telecommunication and computing
applications
Pin and function compatible to MPC949
For functional replacement use 8T49N285A
MPC9449
DATASHEET
3.5 V/2.5 V 1:15
PECL/LVCMOS
CLOCK FANOUT BUFFER
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
Functional Description
The MPC9449 is specifically designed to distribute LVCMOS compatible clock
signals up to a frequency of 200 MHz. The device has 15 identical outputs,
organized in four output banks. Each output bank provides a retimed or
frequency divided copy of the input signal with a near zero skew. The output
buffer supports driving of 50
terminated transmission lines on the incident edge: each output is capable of driving either one
parallel terminated or two series terminated transmission lines.
Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In
addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the
OE control will force the outputs into high-impedance mode.
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports
a 2.5 V or 3.3 V power supply and an ambient temperature range of –40C to +85C. The MPC9449 is pin and function
compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.
MPC9449 REVISION 6 MARCH 15, 2016
1
©2016 Integrated Device Technology, Inc.
MPC9449 Data Sheet
3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER
PACKAGE DIMENSIONS
DSELA
V
CC
CCLK0
CCLK1
CCLK_SEL
V
CC
PCLK
PCLK
0
1
0
1
0
1
QA0
QA1
QB0
1
2
0
1
QB1
QB2
QC0
0
1
QC1
QC2
QC3
PCLK_SEL
DSELB
DSELC
0
1
QD0
QD1
QD2
QD3
QD4
QD5
DSELD
MR/OE
Figure 1. MPC9449 Logic Diagram
NC
GND
QC0
V
CC
QC1
GND
QC2
V
CC
QC3
GND
GND
QD5
NC
NC
V
CC
QB2
GND
QB1
V
CC
QB0
GND
GND
QA1
V
CC
QA0
GND
39 38 37 36 35 34 33 32 31 30 29 28 27
26
40
25
41
24
42
23
43
44
45
46
47
48
49
50
51
52
22
21
20
MPC9449
19
18
17
16
15
14
5 6 7 8 9 10 11 12 13
NC
V
CC
QD4
GND
QD3
V
CC
QD2
GND
QD1
V
CC
QD0
GND
NC
1
2
3
4
Figure 2. PC9449 52-Lead Package Pinout
(Top View)
MPC9449 REVISION 6 MARCH 15, 2016
MR/OE
CCLK_SEL
V
CC
CCLK0
CCLK1
PCLK
PCLK
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
GND
2
©2016 Integrated Device Technology, Inc.
MPC9449 Data Sheet
3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER
Table 1. Function Table
Control
PCLK_SEL
CCLK_SEL
DSELA, DSELB,
DSELC, DSELD
MR/OE
Default
0
0
00
00
1
0
LVCMOS clock input selected (CCLK0 or CCLK1)
CCLK0 selected
1
Outputs enabled
1
PCLK differential input selected
CCLK1 selected
2
Outputs disabled (high impedance)
Table 2. Pin Configuration
Pin
PCLK, PCLK
CCLK0, CCLK1
PCLK_SEL
CCLK_SEL
DSELA, DSELB, DSELC, DSELD
MR/OE
QA0-1, QB0-2, QC0-3, QD0-5
GND
V
CC
I/O
Input
Input
Input
Input
Input
Input
Output
Supply
Supply
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
CC
Differential LVPECL clock input
LVCMOS clock inputs
LVPECL clock input select
LVCMOS clock input select
Clock divider selection
Output enable/disable (high-impedance tristate)
Clock outputs
Negative power supply (GND)
Positive power supply for I/O and core. All V
CC
pins must be connected to the
positive power supply for correct operation
Function
Table 3. General Specifications
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Power Dissipation Capacitance
Input Capacitance
200
2000
200
12
4.0
Min
Typ
V
CC
2
Max
Unit
V
V
V
mA
pF
pF
Per output
Inputs
Condition
Table 4. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.8
V
CC
0.3
V
CC
0.3
20
50
125
Unit
V
V
V
mA
mA
C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
MPC9449 REVISION 6 MARCH 15, 2016
3
©2016 Integrated Device Technology, Inc.
MPC9449 Data Sheet
3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER
Table 5. DC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= –40
C to 85°C)
Symbol
V
IH
V
IL
V
OH
V
PP
V
CMR(2)
V
OL
Z
OUT
I
IN
I
CCQ
Characteristics
Input High Voltage
Input Low Voltage
Output High Voltage
Peak-to-Peak Input Voltage
Common Mode Range
Output Low Voltage
Output Impedance
Input Current
Maximum Quiescent Supply Current
14 – 17
200
10
PCLK, PCLK
PCLK, PCLK
2.4
250
1.0
V
CC
–0.6
0.55
0.30
Min
2.0
Typ
Max
V
CC
0.3
0.8
Unit
V
V
V
mV
V
V
V
A
mA
V
IN
= V
CC
or GND
All V
CC
Pins
Condition
LVCMOS
LVCMOS
I
OH
= –24 mA
(1)
LVPECL
LVPECL
I
OL
= 24 mA
I
OL
= 12 mA
1. The MPC9449 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
series terminated transmission lines.
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(DC) specification.
Table 6. AC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= –40
C to 85°C)
(1)
Symbol
V
PP
V
CMR(2)
f
max
f
ref
t
P, REF
t
r
, t
f
t
sk(O)
Characteristics
Peak-to-Peak Input Voltage
Common Mode Range
Output Frequency
Input Frequency
Reference Input Pulse Width
CCLK0, CCLK1 Input Rise/Fall Time
Output-to-Output Skew
Qa outputs
Qb outputs
Qc outputs
Qd outputs
All outputs
All outputs
2.5
250
CCLK0 or CCLK1 to any Q
PCLK to any Q
OE to any Q
OE to any Q
0.1
RMS (1
)
TBD
1.0
1.0
3.0
3.0
5.0
5.0
11
11
1.0
PCLK, PCLK
PCLK, PCLK
Min
400
1.0
0
0
1.5
1.0
50
50
50
100
200
300
Typ
Max
1000
V
CC
–0.6
200
200
Unit
mV
V
MHz
MHz
ns
ns
ps
ps
ps
ps
ps
ps
ns
ps
ns
ns
ns
ns
ns
ps
0.55 to 2.4 V
DC
REF
= 50%
0.8 to 2.0 V
Condition
LVPECL
LVPECL
Same Frequency
Different Frequencies
t
sk(PP)
t
sk(P)
t
PLH
,
HL
t
PLZ, HZ
t
PZL, LZ
t
r
, t
f
t
JIT(CC)
Device-to-Device Skew
Output Pulse Skew
Propagation Delay
Output Disable Time
Output Enable Time
Output Rise/Fall Time
(3)
Cycle-to-Cycle Jitter
1. AC characteristics apply for parallel output termination of 50
to V
TT
.
2. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts propagation delay.
3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition.
MPC9449 REVISION 6 MARCH 15, 2016
4
©2016 Integrated Device Technology, Inc.
MPC9449 Data Sheet
3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER
Table 7. DC Characteristics
(V
CC
= 2.5 V ± 5%, T
A
= –40
C to 85°C)
Symbol
V
IH
V
IL
V
PP
V
CMR(1)
V
OH
V
OL
Z
OUT
I
IN
I
CC
Characteristics
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output Impedance
Input Current
(3)
Maximum Quiescent Supply Current
17–20
200
10
PCLK, PCLK
PCLK, PCLK
Min
1.7
–0.3
250
1.0
1.8
0.6
V
CC
–0.6
Typ
Max
V
CC
0.3
0.7
Unit
V
V
mV
V
V
V
A
mA
V
IN
= V
CC
or GND
All V
CC
Pins
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
I
OH
= –15 mA
(2)
I
OL
= 15 mA
1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(DC) specification.
2. The MPC9449 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of V
TT
.
3. Inputs have pull-down or pull-up resistors affecting the input current.
Table 8. AC Characteristics
(V
CC
= 2.5 V ± 5%, T
A
= -40
C to 85°C)
(1)
Symbol
V
PP
V
CMR(2)
f
max
f
ref
t
P, REF
tr, tf
t
sk(O)
Characteristics
Peak-to-Peak Input Voltage
Common Mode Range
Output Frequency
Input Frequency
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Output-to-Output Skew
Qa outputs
Qb outputs
Qc outputs
Qd outputs
All outputs
All outputs
5.0
350
CCLK0 or CCLK1 to any Q
PCLK to any Q
OE to any Q
OE to any Q
0.1
RMS (1
)
TBD
1.0
1.0
3.5
3.5
7.0
7.0
11
11
1.0
PCLK, PCLK
PCLK, PCLK
Min
400
1.2
0
0
1.5
1.0
50
50
50
100
200
300
Typ
Max
1000
V
CC
–0.6
200
200
Unit
mV
V
MHz
MHz
ns
ns
ps
ps
ps
ps
ps
ps
ns
ps
ns
ns
ns
ns
ns
ps
0.6 to 1.8 V
DC
REF
= 50%
0.7 to 1.7 V
Condition
LVPECL
LVPECL
Same Frequency
Different Frequencies
t
sk(PP)
t
SK(P)
t
PLH, HL
t
PLZ, HZ
t
PZL, LZ
t
r
, t
f
t
JIT(CC)
Device-to-Device Skew
Output Pulse Skew
Propagation Delay
Output Disable Time
Output Enable Time
Output Rise/Fall Time
(3)
Cycle-to-Cycle Jitter
1. AC characteristics apply for parallel output termination of 50
to V
TT
.
2. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts propagation delay.
3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition.
MPC9449 REVISION 6 MARCH 15, 2016
5
©2016 Integrated Device Technology, Inc.
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