INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT109
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1997 Nov 25
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
FEATURES
•
J, K inputs for easy D-type flip-flop
•
Toggle flip-flop or “do nothing” mode
•
Output capability: standard
•
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT109
(S
D
) and reset (R
D
) inputs; also complementary Q and Q
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency
input capacitance
power dissipation
capacitance per flip-flop
notes 1 and 2
C
L
= 15 pF;
V
CC
= 5 V
15
12
12
75
3.5
20
17
14
15
61
3.5
22
ns
ns
ns
MHz
pF
pF
CONDITIONS
HC
HCT
UNIT
1997 Nov 25
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
PIN DESCRIPTION
PIN NO.
1, 15
2, 14, 3, 13
4, 12
5, 11
6, 10
7, 9
8
16
SYMBOL
1R
D
, 2R
D
1J, 2J, 1K, 2K
1CP, 2CP
1S
D
, 2S
D
1Q, 2Q
1Q, 2Q
GND
V
CC
NAME AND FUNCTION
74HC/HCT109
asynchronous reset-direct input (active LOW)
synchronous inputs; flip-flops 1 and 2
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop outputs
complement flip-flop outputs
ground (0 V)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1997 Nov 25
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
FUNCTION TABLE
OPERATING
MODE
asynchronous set
asynchronous reset
undetermined
toggle
load “0” (reset)
load “1” (set)
hold “no change”
Notes
INPUTS
S
D
L
H
L
H
H
H
H
R
D
H
L
L
H
H
H
H
CP
X
X
X
↑
↑
↑
↑
J
X
X
X
h
l
h
l
74HC/HCT109
OUTPUTS
K
X
X
X
l
l
h
h
Q
H
L
H
q
L
H
q
Q
L
H
H
q
H
L
q
Fig.4 Functional diagram.
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time
prior to the LOW-to-HIGH CP transition
X = don’t care
↑
= LOW-to-HIGH CP transition
handbook, full pagewidth
Q
C
K
Q
J
C
C
C
C
C
C
C
S
R
C
CP
C
MBK217
Fig.5 Logic diagram (one flip-flop).
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
1997 Nov 25
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
SYMBOL
PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
propagation delay
nS
D
to nQ
propagation delay
nS
D
to nQ
propagation delay
nR
D
to nQ
propagation delay
nR
D
to nQ
output transition
time
80
16
14
80
set or reset pulse
16
width HIGH or LOW
14
70
removal time
14
nS
D
, nR
D
to nCP
12
clock pulse width
HIGH or LOW
set-up time
nJ, nK to nCP
hold time
nJ, nK to nCP
maximum clock
pulse frequency
70
14
12
5
5
5
6.0
30
35
74HC
+25
typ.
50
18
14
30
11
9
41
15
12
41
15
12
39
14
11
19
7
6
19
7
6
14
5
4
19
7
6
17
6
5
0
0
0
22
68
81
max.
175
35
30
120
24
20
155
31
26
185
37
31
170
34
29
75
15
13
100
20
17
100
20
17
90
18
15
90
18
15
5
5
5
5.0
24
28
5
−40
to
+85
min.
max.
220
44
37
150
30
26
195
39
33
230
46
39
215
43
37
95
19
16
120
24
20
120
24
20
105
21
18
105
21
18
5
5
5
4.0
20
24
−40
to
+125
min.
max.
265
53
45
180
36
31
235
47
40
280
56
48
255
51
43
110
22
19
ns
UNIT
74HC/HCT109
TEST CONDITIONS
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PLH
ns
Fig.7
t
PHL
ns
Fig.7
t
PHL
ns
Fig.7
t
PLH
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6
t
W
ns
Fig.6
t
W
ns
Fig.7
t
rem
ns
Fig.7
t
su
ns
Fig.6
t
h
ns
Fig.6
f
max
MHz
Fig.6
1997 Nov 25
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