DS1806
Digital Sextet Potentiometer
www.dalsemi.com
FEATURES
§
Six digitally controlled 64-position
potentiometers
§
3-wire serial port provides for reading and
setting each potentiometer
§
Devices can be cascaded for single processor
multi-device control
§
Standard resistance values:
- DS1806-010
10 kΩ
- DS1806-050
50 kΩ
- DS1806-100
100 kΩ
§
Operating Temperature Range:
- Industrial temperature: -40° to +85°
C
C
PIN ASSIGNMENT
W1
W2
L1-3
W3
W4
L4-6
W6
RST
CLK
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
H1
H2
H3
H4
H5
W5
H6
D
IN
C
OUT
PIN DESCIPTION
V
CC
RST
D
IN
CLK
C
OUT
H1 - H6
W1 - W6
GND
L1-3
L4-6
-
-
-
-
-
-
-
-
-
-
3V or 5V Supply
Serial Port Reset Input
Serial Port Data Input
Serial Port Clock Input
Cascade Data Output
High End terminal of Pot
Wiper Terminal of Pot
Ground
Low Terminal Pots 1 through 3
Low Terminal Pots 4 through 6
DS1806 20-Pin DIP (300-mil)
DS1806S 20-Pin SOIC (300-mil)
DS1806E 20-Pin TSSOP (173-mil)
See Mech. Drawings Section
DESCRIPTION
The DS1806 Digital Sextet Potentiometer is a six-channel, digitally controlled, solid-state linear
potentiometer. Each potentiometer is comprised of 63 equiresistive sections as illustrated in the block
diagram of Figure 1. Each potentiometer has three terminals accessible to the user. These include the high
side terminals, H
X
, the wiper terminals, W
X
, and the low-end terminals, L1-3 and L4-6. Potentiometers 1
through 3 share the same low-end terminal L1-3; likewise, potentiometers 4 through 6 share the low-end
terminal L4-6.
Each wiper’ position is selected via an 8-bit register value. Communication and control of the device is
s
accomplished via a 3-wire serial port interface. This interface in conjunction with a cascade output allows
the value of the device wiper settings to be read.
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For multiple device and single processor environments, the DS1806 can be cascaded or daisy-chained.
This feature allows a single processor to control multiple devices.
The DS1806 is available in 10, 50 and 100-kohm versions and is specified over the industrial temperature
range. Packages for the device include 20-lead DIPs, SOICs, and TSSOPs.
OPERATION
A block diagram of the device is provided in Figure 1. As shown, the DS1806 contains six 64-position
potentiometers whose wiper positions are set by an 8-bit value. The DS1806 contains a 48-bit I/O shift
register which is used to store the respective wiper position data for each of the six potentiometers.
Each potentiometer has three terminals accessible to the user. These include the high side terminals, H
X
,
the wiper terminals, W
X
, and the low-end terminals, L1-3 and L4-6. Potentiometers 1 through 3 share the
same low-end terminal L1-3. And likewise, potentiometers 4 through 6 share the low-end terminal L4-6.
Control of the DS1806 is accomplished via a 3-wire serial communication interface which allows the user
to set the wiper position value for each potentiometer. The 3-wire serial interface consists of the control
signals
RST
, D
IN
, and CLK. On power-up, the wiper positions of each potentiometer are set to the low-
end terminal L
X
(00000000).
The
RST
control signal is used to enable 3-wire serial port operation. The
RST
signal (3-wire serial port)
is active when in a high state. Any communication intended to change wiper settings must begin with the
transition of the
RST
from the low state to the high state.
The CLK signal input is used to provide timing synchronization for data input and output. Wiper position
data is loaded into the DS1806 through the D
IN
input terminal. This data is shifted one bit at a time into
the 48-bit I/O shift register of the part, LSB first. Figure 3 provides an illustration of the 48-bit shift
register.
Figure 4 provides 3-wire serial port protocol and timing diagrams. As shown, the 3-wire port is inactive
when the
RST
signal input is low. Once
RST
has transitioned from the low to the high state, the serial
port becomes active. When active, data is loaded into the I/O shift register on the low-to-high transition of
the CLK.
Data is transmitted in order of LSB first. Potentiometers are designated from 1 through 6 and the value
for potentiometer-1 will be the first data entered into the shift register, followed by that of potentiometer-
2 and so forth.
Each wiper has an 8-bit register which is used for setting the position of the wiper on the resistor array.
Because the DS1806 is a 64-position potentiometer, only six bits of information are needed to set wiper
position. The remaining two bits of information are used to provide a “don’ change” feature. Wiper
t
position is controlled by bit positions 0 through 5 of each register. The “don’ change” feature is
t
controlled by bits 6 and 7 of each register. When bits 6 and 7 have value “11 xxxxxx,” wiper position will
not change regardless of the states of bits 0 through 5. If bits 6 and 7 are set to any other value, bits 0
through 5 will be used as the new wiper position. The “don’ change” feature allows the user to change
t
the value of any potentiometer of the DS1806 without affecting or having to remember the remaining
positions of the potentiometer wipers. Figure 2 provides the format for a wiper’ register.
s
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Wiper placement for each potentiometer is such that position-63 corresponds to the H
X
terminal of the de-
vice while position-0 corresponds to the ground terminal. For example, to set a potentiometer’ wiper
s
position to 15 (decimal), the binary value shifted into the wiper register should be 00001111. This will
place the wiper tap at the 15
th
step above the low-end terminal, L
X
.
All communication transactions should provide the total 48 bits of information when writing or reading
from the part. This is especially true for applications using all six potentiometers. If a complete set of 48
bits is not transmitted to the part, undesired wiper position settings may occur.
DS1806 BLOCK DIAGRAM
Figure 1
WIPER REGISTER CONFIGURATION
Figure 2
48-BIT I/O SHIFT REGISTER
Figure 3
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3-WIRE SERIAL PORT TIMING
Figure 4
CASCADE OPERATION
A feature of the DS1806 is the ability to control multiple devices from a single processor. Multiple
DS1806s can be linked or daisy chained as shown in Figure 5. As a data bit is entered into the I/O shift
register of the DS1806, a bit will appear at the C
OUT
terminal before a maximum delay of 50 nanoseconds.
The LSB of potentiometer-1 will always be the first out of the part at the beginning of a transaction.
Additionally, the C
OUT
terminal is always active regardless of the state
RST
. However, D
IN
and CLK
inputs are ignored when
RST
is in the low state.
The C
OUT
output of the DS1806 can be used to drive the D
IN
input of another DS1806. When cascading
multiple devices, the total number of bits transmitted is always 48 multiplied by the total number of
DS1806s being cascaded.
An optional feedback resistor can be placed between the C
OUT
terminal of the last device and the first
DS1806 D
IN
input, which allows the controlling processor to read as well as write data or circularly clock
data through the daisy chain. The value of the feedback or isolation resistor should be in the range from 1
kΩ to 10 kΩ .
To read data, the reading device configures itself as an input and monitors the state of the D
IN
line, which
is driven by C
OUT
through the isolation resistor. When
RST
is driven high, bit 48 is present on the C
OUT
pin, which is fed back to the input D
IN
pin through the isolation resistor. When the CLK input transitions
low to high, bit 48 is loaded into the first position of the I/O shift register and bit 47 becomes present on
C
OUT
and D
IN
of the next device. After 48 bits (or 48 times the number of the DS1806s in the daisy
chain), the data has shifted completely around and back to its original position. When
RST
transitions to
the low state to end data transfer, the value (the same as before the read occurred) is loaded in the shift
register.
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity is defined as the difference between the actual measured output voltage and the
expected output voltage. Absolute linearity is given in terms of a minimum increment or expected output
when the wiper is moved one position. The DS1806 is specified to have an absolute linearity of
±0.50
LSB.
Relative linearity is a measure of error between two adjacent wiper position points. The DS1806 is
specified to have a relative linearity of
±0.25
LSB.
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TYPICAL APPLICATION CONFIGURATIONS
Figure 6 shows the typical application configuration of the DS1806 as a fixed gain attenuator. In this
configuration, the DS1806 adjusts the attenuation level of the incoming signal. Variations in wiper
resistance are minimized by connecting the wiper terminal of the part to a high impedance load.
Depending on voltage across the wiper, its resistance may vary from 400 ohms to 1000 ohms. Note that
the resistance R1 in Figure 6 should be chosen to be much greater than the wiper resistance R
W
.
CASCADING MULTIPLE DEVICES
Figure 5
FIXED GAIN ATTENUATOR
Figure 6
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