Programmable FemtoClock
®
NG
ICS83PN128I
Differential-to-3.3V, 2.5V LVPECL Synthesizer
DATA SHEET
General Description
The ICS83PN128I is a programmable LVPECL synthesizer that can
be used for frequency conversions. The device uses IDT’s fourth
generation FemtoClock
®
NG technology for optimal high clock
frequency and low phase noise performance, combined with a low
power consumption and high power supply noise rejection.
Oscillator-level performance is maintained with IDT’s Fourth
Generation FemtoClock
®
NG PLL technology, which delivers low
rms phase jitter.
The ICS83PN128I defaults to 161.132813MHz output using a
156.25MHz input with two select pins floating (pulled up with internal
pullup resistors) but can also be set to four different frequency
multiplier settings to support a wide variety of applications. The
below table shows some of the more common application settings.
Features
•
•
•
•
•
•
•
•
•
•
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Fourth Generation FemtoClock
®
NG technology
Footprint compatible with 5mm x 7mm differential oscillators
One differential LVPECL output pair
CLK, nCLK input pair can accept the following levels: HCSL,
LVDS, LVPECL, LVHSTL
Output frequency: 128.90MHz or 161.132813MHz
VCO range: 2.0GHz – 2.5GHz
Cycle-to-cycle jitter: 18ps (typical)
RMS phase jitter @ 128.90MHz, 12kHz – 20MHz: 0.53ps (typical)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Frequency Select Table
FSEL[1:0]
00
01
10
11 (default)
Input
156.25
156.25
156.25
156.25
Output Frequency (MHz)
128.90
128.90
128.90
161.132813
OE
1
Pin Assignment
10
FSEL1
Reserved
2
V
EE
3
4
nCLK
FSEL0
9
8
V
CC
7
nQ
5
CLK
6
Q
ICS83PN128I
10-Lead VFQFN
5mm x 7mm x 1mm package body
K Package
Top View
Block Diagram
Q
CLK
Pulldown
nCLK
Pullup/Pulldown
÷P
Phase
Detector
FemtoClock
®
NG
VCO
÷N
nQ
÷M
2
FSEL[1:0]
Pullup
OE
Pullup
ICS83PN128AKI REVISION A MAY 9, 2013
1
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5
6, 7
8
9
10
Name
OE
Reserved
V
EE
nCLK
CLK
Q, nQ
V
CC
FSEL0
FSEL1
Reserved
Power
Input
Input
Output
Power
Input
Input
Pullup
Pullup
Pullup/
Pulldown
Pulldown
Type
Pullup
Description
Output enable. External pullup required for normal operation.
LVCMOS/LVTTL interface levels.
Reserved pin.
Negative supply pin.
Inverting differential clock input. V
CC
/2 default when left floating
Non-inverting differential clock input.
Differential output pair. LVPECL interface levels.
Power supply pin.
Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3,
Frequency Select Table.
Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3,
Frequency Select Table.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. P, M, N Divider Function Table
FSEL[1:0]
00
01
10
1 1 (default)
P Divider
÷2
÷2
÷2
÷2
M Divider
26.39872
26.39872
26.39872
33.00
N Divider
÷16
÷16
÷16
÷16
Input Frequency (MHz)
156.25
156.25
156.25
156.25
Output Frequency (MHz)
128.90
128.90
128.90
161.132813
ICS83PN128AKI REVISION A MAY 9, 2013
2
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
39.2C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
189
Units
V
mA
Table 4B. Power Supply DC Characteristics, V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
182
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics, V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
OE,
FSEL[1:0]
OE,
FSEL[1:0]
V
CC
= 3.465V
V
CC
= 2.625V
Input High Current
Input Low Current
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
ICS83PN128AKI REVISION A MAY 9, 2013
3
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Table 4D. Differential DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High Current CLK, nCLK
CLK
I
IL
Input Low Current
nCLK
V
PP
V
CMR
Peak-to-Peak Voltage
Common Mode Input Voltage;
NOTE 1
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
IN
= 0V,
V
CC
= 3.465V or 2.625V
V
IN
= 0V,
V
CC
= 3.465V or 2.625V
-5
-150
0.15
V
EE
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: Common mode input voltage is defined at the cross point.
Table 4E. LVPECL DC Characteristics, V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage
Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.8
V
CC
– 1.6
1.0
Units
V
V
V
NOTE 1: Outputs termination with 50 to V
CC
– 2V.
ICS83PN128AKI REVISION A MAY 9, 2013
4
©2013 Integrated Device Technology, Inc.
ICS83PN128I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
AC Electrical Characteristics
Table 6A. AC Characteristics, V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
tjit(cc)
Parameter
Output Frequency
FSEL[1:0] = 11
Cycle-to-Cycle Jitter; NOTE 1
128.90MHz,
Integration Range: 12kHz – 20MHz
161.132813MHz,
Integration Range: 12kHz – 20MHz
20% to 80%
150
49
161.132813
18
0.53
0.374
450
51
30
MHz
ps
ps
ps
ps
%
Test Conditions
FSEL[1:0] = 00
Minimum
Typical
128.90
Maximum
Units
MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise plots. Measured using low noise input source.
Table 6B. AC Characteristics, V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
tjit(cc)
Parameter
Output Frequency
FSEL[1:0] = 11
Cycle-to-Cycle Jitter; NOTE 1
128.90MHz,
Integration Range: 12kHz – 20MHz
161.132813MHz,
Integration Range: 12kHz – 20MHz
20% to 80%
100
49
161.132813
18
0.56
0.374
500
51
35
MHz
ps
ps
ps
ps
%
Test Conditions
FSEL[1:0] = 00
Minimum
Typical
128.90
Maximum
Units
MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise plots. Measured using low noise input source.
ICS83PN128AKI REVISION A MAY 9, 2013
5
©2013 Integrated Device Technology, Inc.
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