MC74HC161A,
MC74HC163A
Presettable Counters
High−Performance Silicon−Gate CMOS
The MC74HC161A and HC163A are identical in pinout to the
LS161 and LS163. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC161A and HC163A are programmable 4−bit binary counters
with asynchronous and synchronous reset, respectively.
Features
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MARKING
DIAGRAMS
16
16
1
SOIC−16
D SUFFIX
CASE 751B
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
x
A
WL, L
YY, Y
WW, W
G or
G
= 1 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
HC
16xA
ALYWG
G
HC16xAG
AWLYWW
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
Chip Complexity: 192 FETs or 48 Equivalent Gates
•
These are Pb−Free Devices
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. 13
1
Publication Order Number:
MC74HC161A/D
MC74HC161A, MC74HC163A
RESET
CLOCK
P0
P1
P2
P3
ENABLE P
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RIPPLE
CARRY OUT
Q0
Q1
Q2
Q3
ENABLE T
LOAD
FUNCTION TABLE
Inputs
Clock
Reset*
L
H
H
H
H
Load
X
L
H
H
H
Enable P
X
X
H
L
X
Enable T
X
X
H
X
L
Output
Q
Reset
Load Preset Data
Count
No Count
No Count
*HC163A only. HC161A is an Asynchronous Reset Device
H = high level, L = low level, X = don’t care
Figure 1. Pin Assignment
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK
3
4
5
6
2
14
13
12
11
15
Q0
Q1
Q2
Q3
RIPPLE
CARRY
OUT
BCD OR
BINARY
OUTPUT
RESET
LOAD
COUNT
ENABLES
ENABLE P
ENABLE T
1
9
7
10
PIN 16 = V
CC
PIN 8 = GND
Figure 2. Logic Diagram
DEVICE/MODE TABLE
Device
HC161A
HC163A
Count
Mode
Binary
Binary
Reset Mode
Asynchronous
Synchronous
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2
MC74HC161A, MC74HC163A
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
I
LATCHUP
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Latchup Performance
Oxygen Index: 30%
−
35%
Human Body Model (Note 2)
Machine Model (Note 3)
Above V
CC
and Below GND at 85_C (Note 4)
SOIC
TSSOP
SOIC
TSSOP
(Note 1)
Parameter
Value
*0.5
to
)7.0
*0.5
to V
CC
)0.5
*0.5 v
V
O
v
V
CC
)0.5
$20
$25
$25
$50
$50
*65
to
)150
260
)150
112
148
500
450
Level 1
UL 94 V−0 @ 0.125 in
u2000
u200
$300
V
mA
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 4)
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Parameter
(Referenced to GND)
(Referenced to GND)
Min
2.0
0
*55
0
0
0
0
Max
6.0
V
CC
)125
1000
600
500
400
Unit
V
V
_C
ns
5. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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3
MC74HC161A, MC74HC163A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
3.6 mA
|I
out
|
v
4.0 mA
|I
out
|
v
5.2 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
3.6 mA
|I
out
|
v
4.0 mA
|I
out
|
v
5.2 mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
–55 to 25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±
0.1
4.0
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±
1.0
40
v
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±
1.0
160
mA
mA
V
Unit
V
V
IL
Maximum Low−Level
Input Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level
Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
V
OL
Maximum Low−Level
Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
I
in
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
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4
MC74HC161A, MC74HC163A
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
f
max
Parameter
Maximum Clock Frequency
(50% Duty Cycle)
(Note 6)
Maximum Propagation Delay,
Clock to Q
Figure
4, 10
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
−
Guaranteed Limit
– 55 to 25_C
6
15
30
35
120
75
20
16
145
100
22
18
145
100
20
17
110
60
16
14
135
100
18
15
120
75
22
18
145
100
22
20
155
120
22
18
75
30
15
13
10
v
85_C
5
12
24
28
160
120
23
20
185
135
25
20
185
135
22
19
150
115
18
15
175
130
20
16
160
135
27
22
185
135
28
24
190
140
26
22
95
40
19
16
10
v
125_C
4
10
20
24
200
150
28
22
220
150
30
23
220
150
25
21
190
140
20
17
210
160
22
20
200
150
30
25
220
150
35
28
230
155
30
25
110
55
22
19
10
Unit
MHz
t
PLH
4, 10
ns
t
PHL
4, 10
ns
t
PHL
Maximum Propagation Delay,
Reset to Q (HC161A Only)
5, 10
ns
t
PLH
Maximum Propagation Delay,
Enable T to Ripple Carry Out
6, 10
ns
t
PHL
6, 10
ns
t
PLH
Maximum Propagation Delay,
Clock to Ripple Carry Out
4, 10
ns
t
PHL
4, 10
ns
t
PHL
Maximum Propagation Delay,
Reset to Ripple Carry Out
(HC161A Only)
Maximum Output Transition Time,
Any Output
5, 10
ns
t
TLH
,
t
THL
5, 10
ns
C
in
Maximum Input Capacitance
4, 10
pF
6. Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine f
max
. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the f
max
in the table above is applicable.
See Applications information in this data sheet.
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Gate) (Note 7)
2
f
45
+ I
CC
V
CC
.
pF
7. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
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