MC74HCT14A
Hex Schmitt-Trigger
Inverter with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT14A may be used as a level converter for interfacing
TTL or NMOS outputs to high−speed CMOS inputs.
The HCT14A is useful to “square up” slow input rise and fall times.
Due to the hysteresis voltage of the Schmitt trigger, the HCT14A finds
applications in noisy environments.
Features
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SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 72 FETs or 18 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
A1
1
2
Y1
1
A2
3
4
Y2
14
PIN ASSIGNMENT
A1
Y1
A2
Y2
A3
Y3
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
A6
Y6
A5
Y5
A4
Y4
MARKING DIAGRAMS
14
HCT14AG
AWLYWW
1
SOIC−14 NB
A
L, WL
Y, YY
W, WW
G or
G
TSSOP−14
HCT
14A
ALYWG
G
A3
5
6
Y3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
A4
9
8
Y4
(Note: Microdot may be in either location)
FUNCTION TABLE
A5
11
10
Y5
Input
A
L
H
Output
Y
H
L
A6
13
12
Y6
Y=A
PIN 14 = V
CC
PIN 7 = GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
October, 2014 − Rev. 14
Publication Order Number:
MC74HCT14A/D
MC74HCT14A
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above V
CC
and Below GND at 85_C (Note 4)
SOIC
TSSOP
SOIC
TSSOP
Parameter
(Referenced to GND)
(Referenced to GND)
(Referenced to GND)
Value
−0.5 to +7.0
−0.5 to V
CC
+ 0.5
−0.5 to V
CC
+ 0.5
±20
±25
±25
±50
±50
−65 to +150
260
+150
125
170
500
450
Level 1
UL 94 V−0 @ 0.125 in
> 4000
> 300
> 1000
±300
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
I
Latchup
Latchup Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
, V
O
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Parameter
(Referenced to GND)
(Referenced to GND)
Min
4.5
0
−55
−
Max
5.5
V
CC
+125
(Note 5)
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. No Limit when V
I
[
50% V
CC
, I
CC
> 1 mA.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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2
MC74HCT14A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Temperature Limit
V
CC
Symbol
V
T)
max
V
T)
min
V
T*
max
V
T*
min
V
H
max
V
H
min
V
OH
Parameter
Maximum Positive−Going
Input Threshold Voltage
Minimum Positive−Going
Input Threshold Voltage
Maximum Negative−Going
Input Threshold Voltage
Minimum Negative−Going
Input Threshold Voltage
Maximum Hysteresis
Voltage
Minimum Hysteresis
Voltage
Minimum High−Level
Output Voltage
Test Conditions
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
I
< V
T*
min
|I
out
|
≤
20
mA
V
I
< V
T*
min
|I
out
|
≤
4.0 mA
V
OL
Maximum Low−Level
Output Voltage
V
I
≥
V
T)
max
|I
out
|
≤
20
mA
V
I
≥
V
T)
max
|I
out
|
≤
4.0 mA
I
IK
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per package)
V
I
= V
CC
or GND
V
I
= V
CC
or GND
I
out
= 0
mA
Volts
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
0.4
0.4
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
1.0
0.5
0.6
1.4
1.5
0.4
0.4
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
10
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
0.4
04
4.4
5.4
3.7
0.1
0.1
0.4
±1.0
40
mA
mA
V
V
*55_C
to 25_C
Min
Max
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
v85_C
Min
Max
1.9
2.1
1.2
1.4
1.2
1.4
v125_C
Min
Max
1.9
2.1
Unit
V
V
w*55_C
DI
CC
Additional Quiescent
Supply Current
V
I
= 2.4 V, Any One Input
V
I
= V
CC
or GND, Other Inputs
l
out
= 0
mA
5.5
2.9
25_C to 125_C
2.4
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC CHARACTERISTICS
(C
L
= 50 pF; Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
*55_C
to 25_C
Symbol
Parameter
Test Conditions
Figures
Min
Max
v85_C
Min
Max
v125_C
Min
Max
Unit
t
PLH
,
t
PHL
t
TLH
,
t
THL
Maximum Propagation
Delay, Input A to Output
Y (L to H)
Maximum Output
Transition Time, Any
Output
V
CC
= 5.0 V
±10%
C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns
V
CC
= 5.0 V
±10%
C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns
1&2
32
40
48
ns
1&2
15
19
22
ns
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance, per Inverter (Note 7)
32
pF
7. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
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3
MC74HCT14A
t
f
INPUT A 2.7 V
1.3 V
0.3 V
t
r
3V
GND
t
PLH
90%
1.3 V
10%
t
PHL
OUTPUT Y
t
TLH
t
THL
Figure 1. Switching Waveforms
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance.
Figure 2. Test Circuit
ORDERING INFORMATION
Device
MC74HCT14ADG
NLV74HCT14ADG*
MC74HCT14ADR2G
NLV74HCT14ADR2G*
MC74HCT14ADTR2G
NLV74HCT14ADTR2G*
Package
SOIC−14 NB
(Pb−Free)
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
Shipping
†
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74HCT14A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X
K
REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
_
8
_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0
_
8
_
0.10 (0.004)
0.15 (0.006) T U
S
M
T U
S
V
S
N
2X
L/2
14
8
0.25 (0.010)
M
L
PIN 1
IDENT.
1
7
B
−U−
N
F
DETAIL E
K
0.15 (0.006) T U
S
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T−
SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
14X
0.36
14X
1.26
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÇÇÇ
A
−V−
K1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
0.65
PITCH
DIMENSIONS: MILLIMETERS
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